Substrate treating apparatus

Abstract

A substrate treating method for treating substrates with a substrate treating apparatus having an indexer section, a treating section and an interface section includes performing resist film forming treatment in parallel on a plurality of stories provided in the treating section and performing developing treatment in parallel on a plurality of stories provided in the treating section.

Claims

What is claimed is: 1. A substrate treating method for treating substrates with a substrate treating apparatus having an indexer section, a treating section and an interface section, the method comprising the steps of: performing resist film forming treatment in parallel on at least two of a plurality of stories provided in the treating section, wherein the treating section includes the plurality of stories arranged vertically, each story having: treating units for treating substrates, and a main transport mechanism for transporting the substrates to the treating units on each story; and performing developing treatment in parallel on at least two of the plurality of stories provided in the treating section; a step executed in the interface section of receiving the substrates alternately from the respective stories on which the resist film forming treatment is performed, and transporting the substrates to an exposing machine provided as external apparatus; and a step executed in the interface section of receiving the substrates from the exposing machine, and transporting the substrates alternately to the respective stories on which the developing treatment is performed; wherein the step of transporting the substrates to the exposing machine is realized by an interface's transport mechanism provided for the interface section to repeat, while changing the stories from which the substrates are received, an operation to receive one substrate from one of the stories and transport the substrate to the exposing machine; the step of transporting the substrates alternately to the respective stories is realized by the interface's transport mechanism to repeat, while changing the stories to which the substrates are transported, an operation to receive one substrate from the exposing machine and transport the substrate to one of the stories; and the step of transporting the substrates to the exposing machine is executed to transport the substrates to the exposing machine in an order in which the substrates are taken out of a cassette placed on a cassette table provided for the indexer section. 2. The substrate treating method of claim 1 , comprising the step executed in the indexer section of taking the substrates out of a cassette placed on the cassette table and transporting the substrates alternately to the respective stories on which the resist film forming treatment is performed; the step of transporting the substrates alternately to the respective stories being realized by an indexer's transport mechanism provided for the indexer section to repeat, while changing the stories to which the substrates are transported, an operation to take one substrate out of the cassette and transport the substrate to one of the stories. 3. The substrate treating method of claim 1 , comprising the step executed in the indexer section of receiving the substrates alternately from the respective stories on which the developing treatment is performed, and storing the substrates in a cassette; the step of storing the substrates in the cassette being realized by an indexer's transport mechanism provided for the indexer section to repeat, while changing the stories from which the substrates are received, an operation to receive one substrate from one of the stories and store the substrate in the cassette. 4. The substrate treating method of claim 1 ; wherein both the step of performing the resist film forming treatment and the step of performing the developing treatment are executed on each of the stories; the method further comprising the step executed in the indexer section of taking substrates out of a cassette, transporting the taken-out substrates alternately to the respective stories, and when transporting the substrates to the respective stories, receiving substrates alternately from the respective stories, and storing the received substrates in the cassette; the step being realized by an indexer's transport mechanism provided for the indexer section to repeat, while changing the stories, an operation to store one substrate in the cassette, take one substrate out of the cassette, transport the substrate to one of the stories, and receive one substrate from the one of the stories. 5. The substrate treating method of claim 1 , wherein the step of transporting the substrates to the exposing machine is executed to transport the substrates received from the respective stories on which the resist film forming treatment is performed to the exposing machine, instead of storing the substrates in the cassette placed on the cassette table provided for the indexer section. 6. The substrate treating method of claim 1 , wherein the step of transporting the substrates alternately to the respective stories is executed to transport the substrates received from the exposing machine to the respective stories on which the developing treatment is performed, instead of storing the substrates in the cassette placed on the cassette table provided for the indexer section. 7. The substrate treating method of claim 1 ; wherein both the step of performing the resist film forming treatment and the step of performing the developing treatment are executed on each of the stories; the method further comprising the step executed in the interface section of receiving the substrates alternately from the respective stories, transporting the substrates to an exposing machine provided as external apparatus, receiving the substrates from the exposing machine, transporting the substrates to the respective stories, and when transporting the substrates to the respective stories, receiving the substrates from the respective stories; the step being realized by an interface's transport mechanism provided for the interface section to repeat, while changing the stories, an operation to transport one substrate to one of the stories, receive one substrate from the one of the stories, transport the substrate the exposing machine, and receive one substrate from the exposing machine. 8. The substrate treating method of claim 1 wherein each of the stories for performing the resist film forming treatment of the substrates feeds the substrates to the interface section in an order in which the substrates are received from the indexer section. 9. The substrate treating method of claim 1 wherein each of the stories for performing the developing treatment of the substrates feeds the substrates to the indexer section in an order in which the substrates are received from the interface section. 10. The substrate treating method of claim 1 wherein controls for causing the respective stories to perform the resist film forming treatment of the substrates are independent of each other. 11. The substrate treating method of claim 1 wherein controls for causing the respective stories to perform the developing treatment of the substrates are independent of each other. 12. The substrate treating method of claim 1 wherein the step of performing the resist film forming treatment in parallel is executed to carry out a series of treating steps successively for the substrates, which treating steps include treatment for applying a resist film material to the substrates and treatment for heat-treating the substrates, periods of the series of treating steps being uniformed for the respective substrates. 13. The substrate treating method of claim 1 , comprising: the step executed in the indexer section of taking the substrates out of a cassette, and transporting the substrates to the respective stories on which the resist film forming treatment is performed; and the step executed in the interface section of receiving the substrates from the respective stories on which the resist film forming treatment is performed, and transporting the substrates to an exposing machine provided as external apparatus. 14. The substrate treating method of claim 13 wherein, when a difference occurs between the order of the substrates received by the interface section from the stories on which the resist film forming treatment is performed, and the order of the substrates taken out of the cassette in the indexer section, the substrates are placed on buffers to enable the interface section to receive succeeding substrates from the respective stories on which the resist film forming treatment is performed. 15. The substrate treating method of claim 13 wherein, when the substrates fail to be fed to the interface section from part of the stories on which the resist film forming treatment is performed and the substrates are fed to the interface section from other of the stories, the interface section transports the substrates fed from the other of the stories to the buffers. 16. The substrate treating method of claim 15 wherein, when the substrates begin to be fed again from the part of the stories having stopped feeding the substrates, the interface section transports the substrates fed from the part of the stories and the substrates placed on the buffers, alternately to the exposing machine. 17. The substrate treating method of claim 1 , wherein the main transport mechanism of each story is confined to the story thereof and not shared in adjacent stories. 18. The substrate treating method of claim 1 , wherein the treating section includes a shielding plate disposed between the respective stories. 19. The substrate treating method of claim 1 , wherein: the indexer section transports the substrates between the treating section and a cassette; and the interface section transports the substrates between the treating section and an exposing machine provided as external apparatus.
CROSS-REFERENCES TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 12/163,951, which claims priority to Japanese Patent Application No. 2007-172496, filed Jun. 29, 2007. The disclosures of both of these applications are hereby incorporated by reference in their entirety for all purposes. BACKGROUND OF THE INVENTION (1) Field of the Invention This invention relates to a substrate treating apparatus for performing a series of treatments of substrates such as semiconductor wafers, glass substrates for liquid crystal displays, glass substrates for photomasks, and substrates for optical disks (hereinafter called simply “substrates”). (2) Description of the Related Art Conventionally, a substrate treating apparatus is used to form a resist film on substrates, allows the substrates having the resist film formed thereon to be exposed in a separate exposing machine, and develops the exposed substrates. Specifically, the substrate treating apparatus includes a plurality of blocks each having various chemical treating units such as coating units for forming resist film and heat-treating units arranged with a single main transport mechanism. This apparatus transports substrates to each block to be treated therein (as disclosed in Japanese Unexamined Patent Publication No. 2003-324139, for example). The conventional apparatus with such a construction has the following drawback. In the conventional apparatus, the main transport mechanism goes through five to 10 transporting steps for treating each substrate in its block, and each transporting step takes several seconds. Supposing that the number of transporting steps is six and each step takes five seconds, the throughput in the block can be raised up to 30 seconds per substrate (or 120 substrates per hour). However, there is not much room for reducing the number of transporting steps for the single main transport mechanism or shortening the time for each transporting step. Hence, it is difficult to achieve a further improvement in throughput of each block. It is therefore difficult to improve the throughput of the entire apparatus. One possible solution is to employ multiple main transport mechanisms. However, an increase in the number of main transport mechanisms in each block entails the inconvenience of increasing the chemical treating units and heating units, thereby enlarging the footprint. SUMMARY OF THE INVENTION One of the objectives of this invention is to provide a substrate treating apparatus that can improve throughput without enlarging the footprint of the substrate treating apparatus. In one embodiment, a substrate treating apparatus comprising a plurality of substrate treatment lines each including a plurality of main transport mechanisms arranged horizontally, and a plurality of treating units provided for each of the main transport mechanisms for treating substrates; each of the substrate treatment lines carrying out a series of treatments of the substrates, with each of the main transport mechanisms transporting the substrates to the treating units associated therewith, and transferring the substrates to the other main transport mechanism horizontally adjacent thereto; wherein the substrate treatment lines are arranged vertically. According to this embodiment, the plurality of substrate treatment lines are arranged vertically, so that the substrates are treated in parallel through the respective substrate treatment lines. This realizes an increased throughput of the substrate treating apparatus. Since the substrate treatment lines are arranged vertically, an increase in the installation area of the substrate treating apparatus can be avoided. The horizontal arrangement of the main transport mechanisms is arbitrary. For example, the main transport mechanisms may be arranged in one row or a plurality of rows extending in one direction. The main transport mechanisms may be arranged at different points on an imaginary curve, or may be arranged in a zigzag pattern. The arrangement of the treating units associated with each main transport mechanism is also arbitrary. The treating units may be arranged horizontally, stacked vertically, or arranged crisscross in a matrix form. In an alternate embodiment, the main transport mechanisms and the treating units in the respective substrate treatment lines may be in substantially the same arrangement in plan view. One of the benefits realized by this arrangement is that the apparatus construction can be simplified. The substrate treating apparatus may further comprise gas supply openings for supplying a gas into transporting spaces where the main transport mechanisms are installed, and gas exhaust openings for exhausting the gas from the transporting spaces. This provides the benefit of maintaining the transportation areas substantially free from particulate matter. In addition, the area of the transporting spaces for each substrate treatment line may be blocked off and separate gas supply openings and gas exhaust openings can be provided for each substrate treatment line. This will result in even cleaner transporting spaces. The gas supply openings may be formed in a blowout unit and the gas exhaust openings formed in an exhaust unit with at least one of the gas blowout unit and the gas exhaust unit blocking off atmosphere for each of the substrate treatment lines. This realizes a simplified apparatus construction. The gas supply openings may be arranged in a position higher than the gas exhaust openings further reducing possibility of particulate contamination. The gas supply openings may be arranged over the transporting spaces, and the gas exhaust openings under the transporting spaces. This arrangement results in downward gas currents and helps to keep the transporting spaces cleaner. In still another embodiment, the apparatus may further comprise an indexer's transport mechanism for transporting the substrates to and from a cassette for storing a plurality of substrates, wherein the indexer's transport mechanism transfers the substrates to and from an end transport mechanism which is one of the main transport mechanisms located in one end region of each of the substrate treatment lines, the indexer's transport mechanism transferring the substrates to and from an upper one of the end transport mechanisms at a height adjacent a lower portion of the upper one of the end transport mechanisms, and transferring the substrates to and from a lower one of the end transport mechanisms at a height adjacent an upper portion of the lower one of the end transport mechanisms. Since the upper and lower substrate transfer positions are close to each other, the indexer's transport mechanism moves a reduced amount vertically. This improves the operating efficiency of the indexer's transport mechanism. The apparatus may further comprise a receiver provided between the indexer's transport mechanism and each end transport mechanism for receiving the substrates, the indexer's transport mechanism transferring the substrates through the receiver. The transfer of substrates through the receiver can improve the transporting efficiency over the case of transferring the substrates directly between the transport mechanisms. In yet another embodiment, a substrate treating apparatus comprises a plurality of treating blocks arranged horizontally, each including treating units arranged on each of upper and lower stories, and a main transport mechanism provided for each of the stories for transporting substrates to the treating units on each of the stories; wherein a series of treatments is performed for the substrates by transferring the substrates between the main transport mechanisms of the treating blocks adjacent each other on the same story. According to this embodiment, substrates are transported to and from the plurality of treating blocks arranged horizontally, and in parallel through the different stories. A series of treatments are performed on the substrates in parallel on the respective stories, each having the plurality of treating blocks. This realizes an increased throughput of the substrate treating apparatus. Since the treating blocks have a layered structure with a plurality of stories arranged vertically, an increase in the installation area of the substrate treating apparatus can be avoided. In the embodiment noted above, each of the treating blocks may have a housing for collectively accommodating the treating units and the main transport mechanisms included in each of the treating blocks. Then, each treating block can be handled as a unit, thereby simplifying the manufacture and repair of the substrate treating apparatus. Each of the treating blocks may further include a shielding plate disposed between the respective stories, gas supply openings for supplying a clean gas into a transporting space of the main transport mechanism on each story, and gas exhaust openings for exhausting the gas from the transporting space of the main transport mechanism on each story. This construction can prevent any particles generated by each main transport mechanism from reaching the other story. The transporting space on each story can also be kept clean. In the above construction, the gas supply openings may be formed in a blowout unit, and the gas exhaust openings in an exhaust unit, at least one of the gas blowout unit and the gas exhaust unit acting as the shielding plate. This simplifies the apparatus construction. The gas supply openings of each transporting space may be arranged in a position higher than the gas exhaust openings of the transporting space. Then, the air currents in each transporting space form a down-flow, which can keep the transporting space even cleaner. The apparatus may further comprise an indexer's transport mechanism for transporting the substrates to and from a cassette for storing a plurality of substrates, and for transporting the substrates to the main transport mechanisms on the respective stories of an end one of the treating blocks, wherein the indexer's transport mechanism transfers the substrates, in positions adjacent each other, to and from the main transport mechanisms on the respective stories of the end one of the treating blocks. This enables the indexer's transport mechanism to perform reduced amount of vertical movement, thereby improving the operating efficiency of the indexer's transport mechanism. The above construction may further comprise substrate receivers provided between the main transport mechanisms on the respective stories of the end one of the treating blocks and the indexer's transport mechanism, the indexer's transport mechanism transferring the substrates through each of the receivers. This construction realizes an improved transporting efficiency compared to transferring the substrates directly between the transport mechanisms. In a still another embodiment, a substrate treating apparatus comprises an indexer section including an indexer's transport mechanism for transporting substrates to and from a cassette for storing a plurality of substrates; a coating block disposed adjacent the indexer section, and including coating units and heat-treating units arranged on each of upper and lower stories for forming resist film on the substrates, and a main transport mechanism disposed on each story for transporting the substrates to and from the coating units and the heat-treating units on the each story; a developing block disposed adjacent the coating block, and including developing units and heat-treating units arranged on each of upper and lower stories for developing the substrates, and a main transport mechanism disposed on each story for transporting the substrates to and from the developing units and the heat-treating units on the each story; and an interface section disposed adjacent the developing block, and including an interface's transport mechanism for transporting the substrates to and from an exposing machine provided separately from the apparatus; wherein the indexer's transport mechanism transfers the substrates to and from the main transport mechanism on each story of the coating block; the main transport mechanism on each story of the coating block transfers the substrates to and from the main transport mechanism on the same story of the developing block; and the interface's transport mechanism transfers the substrates to and from the main transport mechanism on each story of the developing block. According to this embodiment, the indexer's transport mechanism takes the substrates out of the cassette in order, and transfers these substrates to the main transport mechanisms on the respective stories of the coating block. Each main transport mechanism of the coating block transports the substrates to the associated coating units and heat-treating units. Each treatment unit carries out a predetermined treatment of the substrates. The main transport mechanism on each story of the coating block transfers the substrates having resist film formed thereon to the main transport mechanism on the same story of the adjoining developing block. Each main transport mechanism of the developing block transfers the substrates to the interface's transport mechanism of the adjoining interface section. The interface's transport mechanism transfers the received substrates to the exposing machine, which is an external apparatus. The exposed substrates are returned to the interface section again. The interface section's transport mechanism transfers the substrates to the main transport mechanism on each story of the developing block. Each main transport mechanism of the developing block transports the substrates to the associated developing units and heat-treating units. Each treating unit carries out a predetermined treatment of the substrates. The main transport mechanism on each story of the developing block transfers the developed substrates the main transport mechanism on the same story of the adjoining coating block. The main transport mechanism on each story of the coating block transfers the substrates to the indexer's transport mechanism of the indexer section. The indexer's transport mechanism stores the substrates in a predetermined cassette. According to this construction, as described above, the coating block and developing block carry out the resist film forming treatment and developing treatment in parallel on each story. This construction, therefore, increases the treating efficiency of the substrate treating apparatus. Since the coating block and developing block have a layered structure with a plurality of stories arranged vertically, an increase in the footprint can be avoided. The apparatus may further comprise a controller for controlling the interface's transport mechanism to transport the substrates to the exposing machine in an order in which the indexer's transport mechanism has taken the substrates out of the cassette. This helps with tracking multiple substrates within the apparatus. The interface section may further include a plurality of buffers to temporarily store the substrates. The controller being arranged to control the interface's transport mechanism, when the substrates are delivered from the developing block in an order different from the order in which the indexer's transport mechanism has taken the substrates out of the cassette, to receive the substrates and transport the substrates to the buffers. The substrates are transferred to the buffers in the event that the substrates are delivered from the developing block in an order different from the order in which the indexer's transport mechanism initially took the substrates out of the cassette. This allows the developing block to deliver succeeding substrates. Further, the order of transporting the substrates from the interface section to the exposing machine may be adjusted to the order in which the indexer's transport mechanism has taken the substrates out of the cassette. Thus, the substrates can be treated conveniently in a predetermined order. The coating units for forming resist film on the substrates may include a resist film coating unit for applying a resist film material to the substrates, and an anti-reflection film coating unit for applying an anti-reflection film forming solution to the substrates. This specification discloses several embodiments directed to the following substrate treating apparatus: (1) A substrate treating apparatus is provided wherein the series of treatments carried out in each of the substrate treatment lines is the same. According to the embodiment defined in (1) above, the apparatus construction can be simplified. (2) A substrate treating apparatus is provided wherein said treating units include solution treating units for treating the substrates with a solution, and heat-treating units for heat-treating the substrates. (3) A substrate treating apparatus is provided in another embodiment wherein said treating units include solution treating units for treating the substrates with a solution, and heat-treating units for heat-treating the substrates. According to the embodiment defined in (2) and (3) above, various treatments can be carried out for the substrates. (4) A substrate treating apparatus is provided further comprising a single, second gas supply pipe for supplying a clean gas to each of the treating units associated with the respective main transport mechanisms arranged vertically. According to the embodiment defined in (4) above, the installation area can be reduced. (5) A substrate treating apparatus is provided in which the main transport mechanisms on the respective stories of each treating block are arranged in the same position in plan view. According to the embodiment defined in (5) above, the apparatus construction can be simplified. (6) A substrate treating apparatus is provided in which the treating units arranged vertically of each treating block perform the same treatment. According to the embodiment defined in (6) above, the apparatus construction can be simplified. (7) A substrate treating apparatus is provided further comprising a single, second gas supply pipe for supplying a clean gas to the treating units arranged vertically. According to the embodiment defined in (7) above, the installation area can be reduced. (8) A substrate treating apparatus is provided wherein the treating units on each story are stacked. According to the embodiment defined in (8) above, the apparatus construction can be simplified. BRIEF DESCRIPTION OF THE DRAWINGS For the purpose of illustrating the invention, there are shown in the drawings several forms which are presently preferred, it being understood, however, that the invention is not limited to the precise arrangement and instrumentalities shown. FIG. 1 is a plan view showing an outline of a substrate treating apparatus according to an embodiment of the present invention; FIG. 2 is a schematic side view showing an arrangement of treating units included in the substrate treating apparatus; FIG. 3 is a schematic side view showing an arrangement of treating units included in the substrate treating apparatus; FIG. 4 is a view in vertical section taken on line a-a of FIG. 1 ; FIG. 5 is a view in vertical section taken on line b-b of FIG. 1 ; FIG. 6 is a view in vertical section taken on line c-c of FIG. 1 ; FIG. 7 is a view in vertical section taken on line d-d of FIG. 1 ; FIG. 8A is a plan view of coating units; FIG. 8B is a sectional view of a coating unit, FIG. 9 is a perspective view of a main transport mechanism; FIG. 10 is a control block diagram of the substrate treating apparatus according to an embodiment of the present invention; FIG. 11 is a flow chart of a series of treatments of wafers W; and FIG. 12 is a view schematically showing operations repeated by each transport mechanism. DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS Embodiments of this invention will be described in detail hereinafter with reference to the drawings. FIG. 1 is a plan view showing an outline of a substrate treating apparatus according to an embodiment of the present invention. FIGS. 2 and 3 are schematic side views showing an arrangement of treating units included in the substrate treating apparatus. FIGS. 4 through 7 are views in vertical section taken on lines a-a, b-b, c-c and d-d of FIG. 1 , respectively. This embodiment provides a substrate treating apparatus for forming resist film on substrates (e.g. semiconductor wafers) W, and developing exposed wafers or substrates W. This apparatus is divided into an indexer section (hereinafter called “ID section”) 1 , a treating section 3 , and an interface section (hereinafter called “IF section”) 5 . The ID section 1 and IF section 5 are arranged adjacent to and on the opposite sides of the treating section 3 . An exposing machine EXP which is an external apparatus separate from this apparatus is disposed adjacent to the IF section 5 . The ID section 1 takes wafers W out of each cassette C, which stores a plurality of wafers W, and deposits wafers W in the cassette C. The ID section 1 has a cassette table 9 for receiving cassettes C and an ID's transport mechanism T ID for transporting wafers W to and from each cassette C. The ID's transport mechanism T ID corresponds to the indexer's transport mechanism in this embodiment. The treating section 3 includes four main transport mechanisms T 1 , T 2 , T 3 and T 4 . The treating section 3 is divided into a first to a fourth cells 11 , 12 , 13 and 14 associated with the respective main transport mechanisms T 1 , T 2 , T 3 and T 4 . The first and third cells 11 and 13 are used for forming resist film on the wafers W. The second and fourth cells 12 and 14 are used for developing the wafers W. Each of the cells 11 - 14 has a plurality of treating units (to be described hereinafter). The main transport mechanisms T 1 , T 2 , T 3 and T 4 transport the wafers W to and from the treating units of the respective cells 11 - 14 . The first and second cells 11 and 12 juxtaposed horizontally are connected to each other to form a substrate treatment line Lu extending between the ID section 1 and IF section 5 . The third and fourth cells 13 and 14 juxtaposed horizontally are also connected to each other to form a substrate treatment line Ld extending between the ID section 1 and IF section 5 . These two substrate treatment lines Lu and Ld are arranged one over the other. In other words, the treating section 3 has a layered structure with the plurality of substrate treatment lines Lu and Ld arranged vertically. The substrate treatment lines Lu and Ld are arranged one over the other to adjoin each other. That is, the first cell 11 is located over the third cell 13 , and the second cell 12 over the fourth cell 14 . Therefore, the treating section 3 may be constructed easily by horizontally arranging a treating block Ba having the first and third cells 11 and 13 formed integrally, and a treating block Bb having the second and fourth cells 12 and 14 formed integrally. The IF section 5 transfers wafers W to and from the exposing machine EXP. The IF section 5 has IF's transport mechanisms T IF for transporting wafers W. The IF's transport mechanisms T IF include a first transport mechanism T IFA and a second transport mechanism T IFB . The first transport mechanism T IFA and second transport mechanism T IFB correspond to the interface's transport mechanisms in this embodiment. The ID's transport mechanism T ID transfers wafers W to and from the main transport mechanisms T 1 and T 3 of the first and third cells 11 and 13 located adjacent the ID section 1 . The main transport mechanisms T 1 -T 4 of the cells 11 - 14 transfer wafers W to and from the other cells connected thereto on the same stories. The IF's transport mechanisms T IF transfer wafers W to and from the main transport mechanisms T 2 and T 4 of the second and fourth cells 12 and 14 located adjacent the IF section 5 . As a result, wafers W are transported between the ID section 1 and IF section 5 in parallel through the two substrate treatment lines Lu and Ld, to undergo a series of treatments in each of the substrate treatment lines Lu and Ld. The main transport mechanisms T 1 and T 3 correspond to the end transport mechanisms in this embodiment. This apparatus includes receivers PASS 1 and PASS 3 for transferring wafers W between the ID's transport mechanism T ID and main transport mechanisms T 1 and T 3 . Similarly, a receiver PASS 2 is provided for transferring wafers W between the main transport mechanisms T 1 and T 2 , and a receiver PASS 4 for transferring wafers W between the main transport mechanisms T 3 and T 4 . Further, receivers PASS 5 and PASS 6 are provided for transferring wafers W between the main transport mechanisms T 2 and T 4 and IF's transport mechanisms T IF . Each of the receivers PASS 1 -PASS 6 has a plurality of support pins projecting therefrom, for receiving a wafer W in a substantially horizontal position on these support pins. [ID Section 1 ] The ID section 1 will be described next. The cassette table 9 can receive four cassettes C arranged in a row. The ID's transport mechanism T ID has a movable base 21 for moving horizontally alongside the cassette table 9 in the direction of arrangement of the cassettes C, a lift shaft 23 vertically extendible and contractible relative to the movable base 21 , and a holding arm 25 swivelable on the lift shaft 23 , and extendible and retractable radially of the swivel motion, for holding a wafer W. The ID's transport mechanism TID can transport wafers W between each cassette C and the receivers PASS 1 and PASS 3 . [First Cell 11 ] A belt-like transporting space A 1 for transporting wafers W extends through the center of the first cell 11 and parallel to the direction of arrangement of the first and second cells 11 and 12 . The treating units of the first cell 11 are coating units 31 for applying a treating solution to the wafers W, and heat-treating units 41 for heat-treating the wafers W. The coating units 31 are arranged on one side of the transporting space A 1 , while the heat-treating units 41 are arranged on the other side thereof. The coating units 31 are arranged vertically and horizontally, each facing the transporting space A 1 . In this embodiment, four coating units 31 in total are arranged in two columns and two rows. The coating units 31 include anti-reflection film coating units BARC for forming anti-reflection film on the wafers W, and resist film coating units RESIST for forming resist film on the wafers W. The coating units 31 correspond to the solution treating units in this embodiment. Reference is made to FIGS. 8A and 8B . FIG. 8A is a plan view of the coating units 31 . FIG. 8B is a sectional view of a coating unit 31 . Each coating unit 31 includes a spin holder 32 for holding and spinning a wafer W, a cup 33 surrounding the wafer W, and a supply device 34 for supplying a treating solution to the wafer W. The two sets of spin holders 32 and cups 33 at each level are juxtaposed with no partition wall or the like in between. The supply device 34 includes a plurality of nozzles 35 , a gripper 36 for gripping one of the nozzles 35 , and a nozzle moving mechanism 37 for moving the gripper 36 to move one of the nozzles 35 between a treating position above the wafer W and a standby position away from above the wafer W. Each nozzle 35 has one end of a treating solution pipe 38 connected thereto. The treating solution pipe 38 is arranged movable to permit movement of the nozzle 35 between the standby position and treating position. The other end of each treating solution pipe 38 is connected to a treating solution source (not shown). Specifically, in the case of antireflection film coating units BARC, the treating solution sources supply different types of treating solution for antireflection film to the respective nozzles 35 . In the case of resist film coating units RESIST, the treating solution sources supply different types of resist film material to the respective nozzles 35 . The nozzle moving mechanism 37 has first guide rails 37 a and a second guide rail 37 b . The first guide rails 37 a are arranged parallel to each other and outwardly of the two cups 33 arranged sideways. The second guide rail 37 b is slidably supported by the two first guide rails 37 a and disposed above the two cups 33 . The gripper 36 is slidably supported by the second guide rail 37 b . The first guide rails 37 a and second guide rail 37 b take guiding action substantially horizontally and in directions substantially perpendicular to each other. The nozzle moving mechanism 37 further includes drive members (not shown) for sliding the second guide rail 37 b , and sliding the gripper 36 . The drive members are operable to move the nozzle 35 gripped by the gripper 36 to the treating positions above the two spin holders 32 . Referring back to FIG. 1 and FIG. 3 , the plurality of heat-treating units 41 are arranged vertically and horizontally, each facing the transporting space A 1 . In this embodiment, three heat-treating units 41 can be arranged horizontally, and five heat-treating units 41 can be stacked vertically. Each heat-treating unit 41 has a plate 43 for receiving a wafer W. The heat-treating units 41 include cooling units CP for cooling wafers W, heating and cooling units PHP for carrying out heating and cooling treatments continually, and adhesion units AHL for heat-treating wafers W in an atmosphere of hexamethyl silazane (HMDS) vapor in order to promote adhesion of coating film to the wafers W. As shown in FIG. 5 , each heating and cooling unit PHP has two plates 43 , and a local transport mechanism (not shown) for moving a wafer W between the two plates 43 . The various types of heat-treating units CP, PHP and AHL are arranged in appropriate positions. Reference is made to FIG. 9 . FIG. 9 is a perspective view of the main transport mechanism T 1 . The main transport mechanism T 1 has two guide rails 51 for providing vertical guidance, and a guide rail 52 for providing horizontal guidance. The vertical guide rails 51 are fixed opposite each other at one side of the transporting space A 1 . In this embodiment, the vertical guide rails 51 are arranged at the side adjacent the coating units 31 . The horizontal guide rail 52 is slidably attached to the vertical guide rails 51 . The horizontal guide rail 52 has a base 53 slidably attached thereto. The base 53 extends transversely, substantially to the center of the transporting space A 1 . Further, drive members (not shown) are provided for vertically moving the horizontal guide rail 52 , and horizontally moving the base 53 . The drive members are operable to move the base 53 to positions for accessing the coating units 31 and heat-treating units 41 arranged vertically and horizontally. The base 53 has a turntable 55 rotatable about a vertical axis Q. The turntable 55 has two holding arms 57 a and 57 b horizontally movably attached thereto for holding wafers W, respectively. The two holding arms 57 a and 57 b are arranged vertically close to each other. Further, drive members (not shown) are provided for rotating the turntable 55 , and moving the holding arms 57 a and 57 b . The drive members are operable to move the turntable 55 to positions opposed to the coating units 31 , heat-treating units 41 and receivers PASS 1 and PASS 2 , and to extend and retract the holding arms 57 a and 57 b to and from the coating units 31 and so on. [Third Cell 13 ] The third cell 13 will be described next. Like reference numerals are used to identify like parts which are the same as in the first cell 11 , and will not be described again. The layout in plan view of the main transport mechanism T 3 and treating units in the third cell 13 is substantially the same as in the first cell 11 . It can be said, therefore, that the coating units 31 are vertically stacked over the different stories of the first cell 11 and third cell 13 . Similarly, it can be said that the heat-treating units 41 also are vertically stacked over the different stories. The arrangement of the various treating units of the third cell 13 as seen from the main transport mechanism T 3 is substantially the same as the arrangement of the various treating units of the first cell 11 as seen from the main transport mechanism T 1 . In the following description, when distinguishing the resist film coating units RESIST in the first and third cells 11 and 13 , subscripts “1” and “3” will be affixed (for example, the resist film coating units RESIST in the first cell 11 will be referred to as “resist film coating units RESIST 1 ”). [First Cell 11 and Third Cell 13 ] Reference is made to FIG. 4 . Constructions relevant to the first cell 11 and third cell 13 will be described collectively. The receiver PASS 1 is disposed between the ID section 1 and first cell 11 . The receiver PASS 3 is disposed between the ID section 1 and third cell 13 . The receivers PASS 1 and PASS 3 are arranged in plan view at the ends of the transporting spaces A 1 and A 3 adjacent the ID section 1 , respectively. Seen in a sectional view, the receiver PASS 1 is disposed at a height adjacent a lower part of the main transport mechanism T 1 , while the receiver PASS 3 is disposed at a height adjacent an upper part of the main transport mechanism T 3 . Therefore, the positions of receiver PASS 1 and receiver PASS 3 are close to each other for allowing the ID's transport mechanism T ID to access the receiver PASS 1 and receiver PASS 3 using only a small amount of vertical movement. Each of the receiver PASS 1 and receiver PASS 3 includes a plurality of (two) receivers arranged one over the other. Of the two receivers PASS 1 , one PASS 1A serves to pass wafers W from the ID's transport mechanism T ID to the main transport mechanism T 1 , and the wafers W are deposited on the receiver PASS 1A solely by the ID's transport mechanism T ID . The other receiver PASS 1B serves to pass wafers W from the main transport mechanism T 1 to the ID's transport mechanism T ID , and the wafers W are deposited on the receiver PASS 1B solely by the main transport mechanism T 1 . Each of the receivers PASS 2 , PASS 4 , PASS 5 and PASS 6 described hereinafter similarly includes two receivers used for transferring wafers W in opposite directions. The receiver PASS 2 is disposed between the first cell 11 and second cell 12 . The receiver PASS 4 is disposed between the third cell 13 and fourth cell 14 . The receivers PASS 2 and PASS 4 are arranged in the same position in plan view. Buffers for temporarily storing wafers W and heat-treating units for heat-treating wafers W (neither being shown) are arranged in appropriate positions above and below the receivers PASS 2 and PASS 4 . Each of the transporting spaces A 1 and A 3 has a first blowout unit 61 for blowing out a clean gas, and an exhaust unit 62 for sucking the gas. Each of the first blowout unit 61 and exhaust unit 62 is in the form of a flat box having substantially the same area as the transporting space A 1 in plan view. Each of the first blowout unit 61 and exhaust unit 62 has first blowout openings 61 a or exhaust openings 62 a formed in one surface thereof. In this embodiment, the first blowout openings 61 a or exhaust openings 62 a are in the form of numerous small bores f. The first blowout units 61 are arranged over the transporting spaces A 1 and A 3 with the first blowout openings 61 a directed downward. The exhaust units 62 are arranged under the transporting spaces A 1 and A 3 with the exhaust openings 62 a directed upward. The atmosphere in the transporting space A 1 and the atmosphere in the transporting space A 3 are blocked off by the exhaust unit 62 of the transporting space A 1 and the first blowout unit 61 of the transporting space A 3 . The first blowout openings 61 a correspond to the gas supply ports in this embodiment. The exhaust openings 62 a correspond to the gas exhaust ports in this embodiment. The first blowout units 61 correspond to the blowout units in this embodiment. Referring to FIG. 5 , the first blowout units 61 of the transporting spaces A 1 and A 3 are connected to a common, first gas supply pipe 63 . The first gas supply pipe 63 extends laterally of the receivers PASS 2 and PASS 4 from an upper position of the transporting space A 1 to a lower position of the transporting space A 3 , and is bent below the transporting space A 3 to extend horizontally. The other end of the first gas supply pipe 63 is connected to a gas source not shown. Similarly, the exhaust units 62 of the transporting spaces A 1 and A 3 are connected to a common, first gas exhaust pipe 64 . The first gas exhaust pipe 64 extends laterally of the receivers PASS 2 and PASS 4 from a lower position of the transporting space A 1 to a lower position of the transporting space A 3 , and is bent below the transporting space A 3 to extend horizontally. As the gas is blown out of each first blowout opening 61 a and sucked and exhausted through each exhaust opening 62 a of the transporting spaces A 1 and A 3 , gas currents are formed to flow from top to bottom of the transporting spaces A 1 and A 3 , thereby keeping each of the transporting spaces A 1 and A 3 in a clean state. Each coating unit 31 of the first and third cells 11 and 13 has a pit portion PS extending vertically. The pit portion PS accommodates a second gas supply pipe 65 extending vertically for supplying the clean gas, and a second gas exhaust pipe 66 extending vertically for exhausting the gas. Each of the second gas supply pipe 65 and second gas exhaust pipe 66 branches at a predetermined height in each coating unit 31 to extend substantially horizontally from the pit portion PS. A plurality of branches of the second gas supply pipe 65 are connected to second blowout units 67 for blowing out the gas downward. A plurality of branches of the second gas exhaust pipe 66 are connected for communication to the bottoms of the respective cups 33 . The other end of the second gas supply pipe 65 is connected to the first gas supply pipe 63 below the third cell 13 . The other end of the second gas exhaust pipe 66 is connected to the first gas exhaust pipe 64 below the third cell 13 . As the gas is blown out of the second blowout units 67 and exhausted through the second exhaust pipes 62 a , the atmosphere inside each cup 33 is constantly maintained clean, thereby allowing for excellent treatment of the wafer W held by the spin holder 32 . The pit portions PS further accommodate piping of the treating solutions, electric wiring and the like (not shown). Thus, with the pit portions PS accommodating the piping and electric wiring provided for the coating units 31 of the first and third cells 11 and 13 , the piping and electric wiring can be reduced in length. The main transport mechanisms T 1 and T 3 and treating units of the first cell 11 and third cell 13 are mounted in one housing 75 . (See FIG. 4 ). This housing 75 defines one treating block Ba. The treating block Ba integrating the first cell 11 and third cell 13 corresponds to the coating block in this embodiment. Similarly, the main transport mechanisms T 2 and T 4 and treating units of the second cell 12 and fourth cell 14 described hereinafter are mounted in a different housing 75 . This housing 75 defines another treating block Bb. The treating block Bb integrating the second cell 12 and fourth cell 14 corresponds to the developing block in this embodiment. Thus, with the housings 75 defining the treating blocks Ba and Bb integrating the cells arranged vertically, the treating section 3 may be manufactured and assembled simply. [Second Cell 12 ] The second cell 12 will be described next. Like reference numerals are used to identify like parts which are the same as in the first cell 11 and will not be described again. The second cell 12 has a transporting space A 2 formed as an extension of the transporting space A 1 . The treating units of the second cell 12 are developing units DEV for developing wafers W, heat-treating units 42 for heat-treating the wafers W, and an edge exposing unit EEW for exposing peripheral regions of the wafers W. The developing units DEV are arranged at one side of the transporting space A 2 , and the heat-treating units 42 and edge exposing unit EEW are arranged at the other side of the transporting space A 2 . Preferably, the developing units DEV are arranged at the same side as the coating units 31 . It is also preferable that the heat-treating units 42 and edge exposing unit EEW are arranged in the same row as the heat-treating units 41 . In one embodiment, the number of developing units DEV is four, and sets of two units DEV arranged horizontally along the transporting space A 2 are stacked one over the other. Each developing unit DEV includes a spin holder 77 for holding and spinning a wafer W, and a cup 79 surrounding the wafer W. The two developing units DEV arranged at the lower level are not separated from each other by a partition wall or the like. A supply device 81 is provided for supplying developers to the two developing units DEV. The supply device 81 includes two slit nozzles 81 a having a slit or a row of small bores for delivering the developers. The slit or row of small bores, preferably, has a length corresponding to the diameter of wafer W. Preferably, the two slit nozzles 81 a are arranged to deliver developers of different types or concentrations. The supply device 81 further includes a moving mechanism 81 b for moving each slit nozzle 81 a . Thus, the slit nozzles 81 a are movable, respectively, over the two spin holders 77 juxtaposed sideways. The plurality of heat-treating units 42 are arranged sideways along the transporting space A 2 , and stacked one over the other. Each heat-treating unit 42 includes a heating unit HP for heating wafers W and a cooling unit CP for cooling wafers W. The single edge exposing unit EEW is disposed in a predetermined position. The edge exposing unit EEW includes a spin holder (not shown) for holding and spinning a wafer W, and a light emitter (not shown) for exposing edges of the wafer W held by the spin holder. The receiver PASS 5 and heating and cooling units PHP are stacked in a position facing the transporting space A 2 and adjacent the IF section 5 . The stack of receiver PASS 5 and heating and cooling units PHP has one side thereof located adjacent one of the heat-treating units 42 , and is aligned with the heat-treating units 42 . As distinct from the heat-treating units 42 of the second cell 12 , the heating and cooling units PHP rely on the IF's transport mechanism TIF for transport of wafers W. In terms of layout, the heating and cooling units PHP are mounted in the same housing 75 as the second and fourth cells 12 and 14 . These heating and cooling units PHP and receiver PASS 5 are constructed for allowing wafers W to be loaded and unloaded through the front thereof opposed to the transporting space A 2 and the side opposed to the IF section 5 . The main transport mechanism T 2 is disposed substantially centrally of the transporting space A 2 in plan view. The main transport mechanism T 2 has the same construction as the main transport mechanism T 1 . The main transport mechanism T 2 transports wafers W to and from the receiver PASS 2 , various heat-treating units 42 , edge exposing unit EEW and receiver PASS 5 . [Fourth Cell 14 ] Like reference numerals are used to identify like parts which are the same as in the first and second cells 11 and 12 , and will not be described again. The layout in plan view of the main transport mechanism T 4 and treating units in the fourth cell 14 is substantially the same as that of the second cell 12 . The arrangement of the various treating units of the fourth cell 14 as seen from the main transport mechanism T 4 is substantially the same as the arrangement of the various treating units of the second cell 12 as seen from the main transport mechanism T 2 . Thus, the developing units DEV of the second cell 12 and fourth cell 14 are stacked vertically. Similarly, the heat-treating units 42 of the second cell 12 and fourth cell 14 are stacked vertically. [Second Cell 12 and Fourth Cell 14 ] Constructions relevant to the second cell 12 and fourth cell 14 also are substantially the same as the constructions relevant to the first cell 11 and third cell 13 , and will be described briefly. Each of the transporting spaces A 2 and A 4 of the second and fourth cells 12 and 14 also has constructions corresponding to the first blowout unit 61 and exhaust unit 62 . Each developing unit DEV of the second and fourth cells 12 and 14 also has constructions corresponding to the second blowout unit 67 and second gas exhaust pipe 66 . In the following description, when distinguishing the developing units DEV, edge exposing units EEW, and so on in the second and fourth cells 12 and 14 , subscripts “2” and “4” will be affixed (for example, the heating units HP in the second cell 12 will be referred to as “heating units HP 2 ”). [IF Section 5 , etc.] Reference is now made to FIG. 1 and FIG. 7 . The first transport mechanism T IFA and second transport mechanism TIFB are arranged in a direction perpendicular to the arrangement of cells 11 and 12 ( 13 and 14 ). The first transport mechanism T IFA is disposed at the side where the heat-treating units 42 and so on of the second and fourth cells 12 and 14 are located. The second transport mechanism T IFB is disposed at the side where the developing units DEV of the second fourth cells 12 and 14 are located. Stacked in multiples stages between the first and second transport mechanisms T IFA and T IFB are a receiver PASS-CP for receiving and cooling wafers W, a receiver PASS 7 for receiving wafers W, and buffers BF for temporarily storing wafers W. The first transport mechanism T IFA includes a fixed base 83 , lift shafts 85 vertically extendible and contractible relative to the base 83 , and a holding arm 87 swivelable on the lift shafts 85 , and extendible and retractable radially of the swivel motion, for holding a wafer W. The first transport mechanism TIFA transports wafers W between the heating and cooling units (PHP 2 , PHP 4 ), receivers (PASS 5 , PASS 6 , PASS-CP) and buffers BF. The second transport mechanism T IFB also has a base 83 , lift shafts 85 and a holding arm 87 for transporting wafers W between the receivers (PASS-CP, PASS 7 ) and exposing machine EXP. A control system of this apparatus will be described next. FIG. 10 is a control block diagram of the substrate treating apparatus according to the embodiment. As shown, this apparatus includes a main controller 91 and a first to a sixth controllers 93 , 94 , 95 , 96 , 97 and 98 . The first controller 93 controls substrate transport by the ID's transport mechanism T ID . The second controller 94 controls substrate transport by the main transport mechanism T 1 , and substrate treatment in the resist film coating units RESIST 1 , antireflection film coating units BARC 1 , cooling units CP 1 , heating and cooling units PHP 1 and adhesion units AHL 1 . The third controller 95 controls substrate transport by the main transport mechanism T 2 , and substrate treatment in the edge exposing unit EEW 2 , developing units DEV 2 , heating units HP 2 and cooling units CP 2 . The controls by the fourth and fifth controllers 96 and 97 correspond to those by the second and third controllers 94 and 95 , respectively. The sixth controller 98 controls substrate transport by the first and second transport mechanisms T IFA and T IFB , and substrate treatment in the heating and cooling units PHP 2 and PHP 4 . The first to sixth controllers 93 - 98 carry out the controls independently of one another. The main controller 91 performs overall control of the first to sixth controllers 93 - 98 . Specifically, the main controller 91 controls coordination among the transport mechanisms. For example, the main controller 91 adjusts the timing of the respective transport mechanisms making access to the receivers PASS 1 -PASS 6 . The main controller 91 also controls wafers W to be transported to the exposing machine EXP in the order in which the wafers W are fetched from the cassettes C. Each of the main controller 91 and the first to sixth controllers 93 - 98 is realized by a central processing unit (CPU) which performs various processes, a RAM (Random Access Memory) used as the workspace for operation processes, and a storage medium such as a fixed disk for storing a variety of information including a predetermined processing recipe (processing program). The main controller 91 and the first to sixth controllers 93 - 98 correspond to the controller in this embodiment. Next, operation of the substrate treating apparatus in this embodiment will be described. FIG. 11 is a flow chart of a series of treatments of wafers W, indicating the treating units and receivers to which the wafers W are transported in order. FIG. 12 is a view schematically showing operations repeated by each transport mechanism, and specifying an order of treating units, receivers and cassettes accessed by the transport mechanisms. The following description will be made separately for each transport mechanism. [ID's Transport Mechanism T ID ] The ID's transport mechanism T ID moves to a position opposed to one of the cassettes C, holds with the holding arm 25 a wafer W to be treated and takes the wafer W out of the cassette C. The ID's transport mechanism T ID swivels the holding arm 25 , vertically moves the lift shaft 23 , moves to a position opposed to the receiver PASS 1 , and places the wafer W on the receiver PASS 1A (which corresponds to step S 1 a in FIG. 11 ; only step numbers will be indicated hereinafter). At this time, a wafer W usually is present on the receiver PASS 1B , and the ID's transport mechanism T ID receives this wafer W and stores it in a cassette C (step S 23 ). When there is no wafer W on the receiver PASS 1B , the ID's transport mechanism T ID just accesses the cassette C. Then, the ID's transport mechanism T ID transports a wafer W from the cassette C to the receiver PASS 3A (step S 1 b ). Here again, if a wafer W is present on the receiver PASS 3B , the ID's transport mechanism T ID will store this wafer W in a cassette C (step S 23 ). The ID's transport mechanism T ID repeats the above operation. This operation is controlled by the first controller 93 . As a result, the wafers W taken out one at a time from the cassette C are transported alternately to the first cell 11 and third cell 13 . [Main Transport Mechanisms T 1 , T 3 ] Since operation of the main transport mechanism T 3 is substantially the same as operation of the main transport mechanism T 1 , only the main transport mechanism T 1 will be described. The main transport mechanism T 1 moves to a position opposed to the receiver PASS 1 . At this time, the main transport mechanism T 1 holds, on one holding arm 57 (e.g. 57 b ), a wafer W received immediately before from the receiver PASS 2B . The main transport mechanism T 1 places this wafer W on the receiver PASS 1B (step S 22 ), and holds the wafer W present on the receiver PASS 1A with the other holding arm 57 (e.g. 57 a ). The main transport mechanism T 1 accesses a predetermined one of the cooling units CP 1 . There is a different wafer W having already received a predetermined heat treatment (cooling) in the cooling unit CP 1 . The main transport mechanism T 1 holds the different wafer W with the unloaded holding arm 57 (holding no wafer W), takes it out of the cooling unit CP 1 , and loads into the cooling unit CP 1 the wafer W having received from the receiver PASS 1A . Then, the main transport mechanism T 1 , holding the cooled wafer W, moves to one of the antireflection film coating units BARC 1 . The cooling unit CP 1 starts heat treatment (cooling) of the wafer W loaded therein (step S 2 ). It is assumed that, when the main transport mechanism T 1 subsequently accesses the different heat-treating units 41 and coating units 31 , wafers W having received predetermined treatments are present in these treating units ( 31 and 41 ). Accessing the antireflection film coating unit BARC 1 , the main transport mechanism T 1 takes a wafer W having antireflection film formed thereon from the antireflection film coating unit BARC 1 , and places the cooled wafer W on the spin holder 32 of the antireflection film coating unit BARC 1 . Then, the main transport mechanism T 1 , holding the wafer W having antireflection film formed thereon, moves to one of the heating and cooling units PHP 1 . The antireflection film coating unit BARC 1 starts treatment of the wafer W placed on the spin holder 32 (step S 3 ). Specifically, the spin holder 32 spins the wafer W in horizontal posture, the gripper 26 grips one of the nozzles 35 , the nozzle moving mechanism 37 moves the gripped nozzle 35 to a position above the wafer W, and the treating solution for antireflection films is supplied from the nozzle 35 to the wafer W. The treating solution supplied spreads all over the wafer W, and is scattered away from the wafer W. The cup 33 collects the scattering treating solution. In this way, the treatment is carried out for forming antireflection film on the wafer W. Accessing the heating and cooling unit PHP 1 , the main transport mechanism T 1 takes a wafer W having received heat treatment out of the heating and cooling unit PHP 1 , and loads the wafer W having antireflection film formed thereon into the heating and cooling unit PHP 1 . Then, the main transport mechanism T 1 , holding the wafer W taken out of the heating and cooling unit PHP 1 , moves to one of the cooling units CP 1 . The heating and cooling unit PHP 1 receives a wafer W successively on the two plates 43 , to heat the wafer W on one of the plates 43 and then to cool the wafer W on the other plate 43 (step S 4 ). Having moved to the cooling unit CP 1 , the main transport mechanism T 1 takes a wafer W out of the cooling unit CP 1 , and loads the wafer W held by the transport mechanism T 1 into the cooling unit CP 1 . The cooling unit CP 1 cools the wafer W loaded therein (step S 5 ). Then, the main transport mechanism T 1 moves to one of the resist film coating units RESIST 1 . The main transport mechanism T 1 takes a wafer W having resist film formed thereon from the resist film coating unit RESIST 1 , and loads the wafer W held by the main transport mechanism T 1 into the resist film coating unit RESIST 1 . The resist film coating unit RESIST 1 supplies the resist film material while spinning the wafer W loaded therein, to form resist film on the wafer W (step S 6 ). The main transport mechanism T 1 further moves to one of the heating and cooling units PHP 1 and one of the cooling units CP 1 . The main transport mechanism T 1 loads the wafer W having resist film formed thereon into the heating and cooling unit PHP 1 , transfers a wafer W treated in the heating and cooling unit PHP 1 to the cooling unit CP 1 , and receives a wafer W treated in the cooling unit CP 1 . The heating and cooling unit PHP 1 and cooling unit CP 1 carry out predetermined treatments of newly loaded wafers W, respectively (steps S 7 and S 8 ). The main transport mechanism T 1 moves to the receiver PASS 2 , places the wafer W it is holding on the receiver PASS 2A (step S 9 ), and receives a wafer W present on the receiver PASS 2B (step S 21 ). Subsequently, the main transport mechanism T 1 accesses the receiver PASS 1 again, and repeats the above operation. This operation is controlled by the second controller 94 . Having received a wafer W from the receiver PASS 1 , the main transport mechanism T 1 transports this wafer W to a predetermined treating unit (a cooling unit CP 1 in this embodiment), and takes a treated wafer W from this treating unit. Subsequently, the main transport mechanism T 1 moves to a plurality of treating units in order, and transfers wafers W treated in the respective treating units to other treating units. Whenever a treated wafer W is replaced by a wafer W to be treated, each treating unit ( 31 , 41 ) starts the predetermined treatment. Thus, predetermined treatments are carried out in parallel for a plurality of wafers W in the respective treating units. A series of treating steps is successively performed for a plurality of wafers W. In these circumstances, the second controller 94 controls periods of the series of treating steps to be uniform. Further, it is preferred to control the timing of transporting wafers W to each treating unit ( 31 , 41 ) and a schedule of treatment carried out in each treating unit ( 31 , 41 ) to be uniform between the wafers W. As a result, the series of treatments is completed in order, starting with a wafer W first placed on the receiver PASS 1 . The wafers W are forwarded to the receiver PASS 2 in the order in which they are placed on the receiver PASS 1 . Similarly, the main transport mechanism T 1 places the wafers W on the receiver PASS 1 in the order of receipt from the receiver PASS 2 . [Main Transport Mechanisms T 2 , T 4 ] Since operation of the main transport mechanism T 4 is substantially the same as operation of the main transport mechanism T 2 , only the main transport mechanism T 2 will be described. The main transport mechanism T 2 moves to a position opposed to the receiver PASS 2 . At this time, the main transport mechanism T 2 holds a wafer W received from a cooling unit CP 2 accessed immediately before. The main transport mechanism T 2 places this wafer W on the receiver PASS 2B (step S 21 ), and holds the wafer W present on the receiver PASS 2A (step S 9 ). The main transport mechanism T 2 accesses the edge exposing unit EEW 2 . The main transport mechanism T 2 receives a wafer W having received a predetermined treatment in the edge exposing unit EEW 2 , and loads the cooled wafer W into the edge exposing unit EEW 2 . While spinning the wafer W loaded therein, the edge exposing unit EEW 2 irradiates peripheral regions of the wafer W with light from the light emitter not shown, thereby exposing the peripheral regions of the wafer W (step S 10 ). The main transport mechanism T 2 , holding the wafer W received from the edge exposing unit EEW 2 , accesses the receiver PASS 5 . The main transport mechanism T 2 places the wafer W on the receiver PASS 5A (step S 11 ), and holds a wafer W present on the receiver PASS 5B (step S 16 ). The main transport mechanism T 2 moves to one of the cooling units CP 2 , and replaces a wafer W in the cooling unit CP 2 with the wafer W held by the main transport mechanism T 2 . The main transport mechanism T 2 holds the wafer W having received cooling treatment, and accesses one of the developing units DEV 2 . The cooling unit CP 2 starts treatment of the newly loaded wafer W (step S 17 ). The main transport mechanism T 2 takes a developed wafer W from the developing unit DEV 2 , and places the cooled wafer W on the spin holder 77 of the developing unit DEV 2 . The developing unit DEV 2 develops the wafer W placed on the spin holder 77 (step S 18 ). Specifically, while the spin holder 77 spins the wafer W in horizontal posture, the developer is supplied from one of the slit nozzles 81 a to the wafer W, thereby developing the wafer W. The main transport mechanism T 2 holds the developed wafer W, and accesses one of the heating units HP 2 . The main transport mechanism T 2 takes a wafer W out of the heating unit HP 2 , and loads the wafer W it is holding into the heating unit HP 2 . Then, the main transport mechanism T 2 transports the wafer W taken out of the heating unit HP 2 to one of the cooling units CP 2 , and takes out a wafer W already treated in this cooling unit CP 2 . The heating unit HP 2 and cooling unit CP 2 carry out predetermined treatments for the newly loaded wafers W, respectively (steps S 19 and S 20 ). Subsequently, the main transport mechanism T 2 accesses the receiver PASS 2 again, and repeats the above operation. This operation is controlled by the third controller 95 . As a result, the wafers W are forwarded to the receiver PASS 5B in the order in which they are placed on the receiver PASS 2A . Similarly, the wafers W are forwarded to the receiver PASS SB in the order in which they are placed on the receiver PASS 5B . [IF's Transport Mechanisms T IF —First Transport Mechanism T IFA ] The first transport mechanism T IFA accesses the receiver PAS S 5 , and receives the wafer W present on the receiver PASS 5A (step S 11 a ). The first transport mechanism T IFA , holding the wafer W received, moves to the receiver PASS-CP, and loads the wafer W on the receiver PASS-CP (step S 12 ). Next, the first transport mechanism T IFA receives a wafer W from the receiver PASS 7 (step S 14 ), and moves to a position opposed to one of the heating and cooling units PHP 2 . The first transport mechanism T IFA takes a wafer W having received heat treatment (PEB: Post Exposure Bake) from the heating and cooling unit PHP 2 , and loads the wafer W received from the receiver PASS 7 into the heating and cooling unit PHP 2 . The heating and cooling unit PHP 2 carries out heat treatment for the newly loaded wafer W (step S 15 ). The first transport mechanism T IFA transports the wafer W taken out of the heating and cooling unit PHP 2 to the receiver PASS 5B . Subsequently, the first transport mechanism T IFA transports a wafer W from the receiver PASS 6A to the receiver PASS-CP (Step S 11 b , 12 ). Next, the first transport mechanism T IFA transports a wafer W from the receiver PASS 7 to one of the heating and cooling units PHP 4 . At this time, the first transport mechanism T IFA takes out a wafer W having been treated in the heating and cooling unit PHP 4 , and places the wafer W on the receiver PASS 6B . Subsequently, the first transport mechanism T IFA accesses the receiver PASS 5 again and repeats the above operation. This operation is controlled by the sixth controller 98 . By transporting wafers W alternately from the receivers PASS 5 and PASS 6 to the receiver PASS-CP, the wafers W are placed on the receiver PASS-CP in the order in which the ID's transport mechanism TID has taken them out of the cassette C. However, the controls of transport to and from the treating units by the main transport mechanisms T and treatment in the treating units are carried out independently for each of the cells 11 - 14 . That is, no adjustment is made to the timing of feeding wafers W to each of the receiver PASS 5 and receiver PASS 6 . Therefore, the order of feeding wafers W to the receiver PASS 5 and receiver PASS 6 may not agree with the order in which they are taken out of the cassette C due to a fault such as a delay in substrate treatment or transportation. In such a case, the sixth controller 98 operates the first transport mechanism T IFA as follows. When wafers W fail to be fed to either one of the receiver PASS 5A and receiver PASS 6A , and wafers W are placed on the other receiver, the wafers W placed on the other receiver is transported to the buffers BF instead of the receiver PASS-CP. When wafers W begin to be placed again on the receiver for which the feeding has been disrupted, the wafers W are transported from the receiver now restored to service to the receiver PASS-CP, and also from the buffers BF to the receiver PASS-CP. At this time, the wafers W are transported alternately from the restored receiver and buffers BF to the receiver PASS-CP. As a result, even when the order of feeding wafers W to the receiver PASS 5 and receiver PASS 6 disagrees with the order in which they are taken out of the cassette C, the order of wafers W transported to the receiver PASS-CP is in agreement with the order of wafers W taken out of the cassette C. [IF's Transport Mechanisms T IF —Second Transport Mechanism T IFB ] The second transport mechanism T IFB takes a wafer W out of the receiver PASS-CP, and transports it to the exposing machine EXP. Then, the second transport mechanism T IFB receives an exposed wafer W from the exposing machine EXP, and transports it to the receiver PASS 7 . Subsequently, the second transport mechanism T IFB accesses the receiver PASS-CP again and repeats the above operation. This operation also is controlled by the sixth controller 98 . As described above, the first and second transport mechanisms T IFA and T IFB cooperate to feed wafers W to the exposing machine EXP in the order in which they are taken out of the cassette C. The substrate treating apparatus according to this embodiment has two substrate treatment lines Lu and Ld arranged one over the other. This construction can substantially double the processing capabilities in the treatment for forming antireflection film and resist film and in the treatment for developing wafers W. Therefore, the throughput of the substrate treating apparatus is improved drastically. Each of the substrate treatment lines Lu and Ld includes the main transport mechanisms T arranged in one row. This arrangement can inhibit an increase in the installation area of the treating section 3 . The arrangements of the main transport mechanisms T 1 and T 3 (T 2 and T 4 ) and treating units in the two, upper and lower, substrate treatment lines Lu (Ld) are substantially the same in plan view, which can simplify the construction of the apparatus. The construction of the apparatus may be simplified by providing the same type of treating units for the two, upper and lower, substrate treatment lines Lu and Ld to perform the same series of treatments. The treating units of the upper and lower cells 11 and 13 ( 12 , 14 ) are stacked together. This arrangement can simplify the construction of treating blocks Ba and Bb each including two, upper and lower cells. Each of the treating blocks Ba and Bb has a housing 75 which collectively supports the two, upper and lower, main transport mechanisms T and the plurality of treating units. This allows the substrate treating apparatus to be manufactured efficiently and to be maintained and repaired easily. Each of the transporting spaces A 1 -A 4 has the first blowout openings 61 a and discharge openings 62 a , which can keep each transporting space A clean. The first blowout openings 61 a are arranged over each transporting space A, and the discharge openings 62 a under each transporting space A, to produce substantially vertical, downward gas currents in the transporting space A. This prevents the temperature environment of transporting spaces A, coating units 31 and developing units DEV from being influenced by the heat from the heat-treating units 41 . The exhaust unit 62 provided in the transporting space A 1 (A 2 ) and the first blowout unit 61 provided in the transporting space A 3 (A 4 ) block off the atmospheres of each of the transporting spaces A 1 and A 3 (A 2 and A 4 ). Thus, each transporting space A can be maintained clean. The apparatus construction is simplified since no special or additional component is required for blocking off atmosphere. The first gas supply pipe 61 is provided as a component common to the first blowout units 61 of the upper and lower transporting spaces A 1 and A 3 . This reduces piping installation space and simplifies the apparatus construction. The receivers PASS 1 and PASS 3 are provided for transferring wafers W between the ID's transport mechanism T ID and main transport mechanisms T 1 and T 3 , which can prevent lowering of the transporting efficiency of the ID's transport mechanism T ID and main transport mechanisms T 1 and T 3 . Similarly, the transporting efficiency of each transport mechanism is prevented from lowering by transferring wafers W between the transport mechanisms through the receivers PASS. Since the receiver PASS 1 and receiver PASS 3 are locate close to each other, the ID's transport mechanism T ID can access the receiver PASS 1 and receiver PASS 3 through a reduced amount of vertical movement. The main controller 91 and the first to sixth controllers 93 - 98 are provided to control movement of wafers W to bring into agreement the order of fetching from a cassette C and the order of feeding to the exposing machine EXP. This enables supervision or follow-up check of each wafer W without providing a construction for identifying the wafers W. The common, second gas supply pipe 65 is provided for the coating units 31 (developing units DEV) in the upper and lower cells 11 and 13 ( 12 and 14 ). This reduces piping installation space and simplifies the apparatus construction. This invention is not limited to the foregoing embodiment, but may be modified as follows: (1) The foregoing embodiment provides two substrate treatment lines Lu and Ld, but the invention not limited to this. The construction may be modified to include three or more substrate treatment lines vertically arranged in multiple stages. (2) In the foregoing embodiment, each substrate treatment line Lu (Ld) has two cells 11 and 12 ( 13 and 14 ) connected to each other. The invention is not limited to this. Each substrate treatment line may have three or more cells. (3) In the foregoing embodiment, the substrate treatment lines Lu and Ld carry out the treatment for forming resist film and antireflection film on the wafers W, and the treatment for developing exposed wafers W. The substrate treatment lines may be modified to perform other treatment such as cleaning of the wafers W. Accordingly, the type, number and the like of treating units are selected or designed as appropriate. Further, the substrate treating apparatus may be constructed to exclude the IF section 5 . (4) In the foregoing embodiment, the two substrate treatment lines Lu and Ld perform the same series of treatments. Instead, the substrate treatment lines Lu and Ld may be modified to perform different treatments. (5) In the foregoing embodiment, the two substrate treatment lines Lu and LD have substantially the same plane layout. Instead, each of the substrate treatment lines Lu and Ld (i.e. upper and lower cells) may have the main transport mechanisms T and treating units arranged differently. (6) In the foregoing embodiment, the upper and lower cells 11 and 13 ( 12 and 14 ) have the same arrangement of treating units as seen from the main transport mechanisms T. Instead, the upper and lower cells may have different arrangements of treating cells. (7) In the foregoing embodiment, each of the cells 11 - 14 has the treating units arranged at opposite sides of the transporting space A. Instead, the treating units may be arranged at only one side. (8) In the foregoing embodiment, wafers W are transferred between the transport mechanisms through the receivers PASS. Instead, the wafers W may be transferred directly between the transport mechanisms, for example. (9) The foregoing embodiment may be modified to include buffers BF and cooling units CP arranged over and/or under the receivers PASS 1 , PASS 2 , PASS 3 and PASS 4 . This construction allows the wafers W to be stored temporarily or cooled as appropriate. (10) In the foregoing embodiment, the IF transport mechanisms TIF include two transport mechanisms TIFA and TIFB. The IF section may be modified to include one transport mechanism or three or more transport mechanisms. (11) The foregoing embodiment provides no partition or the like between the antireflection film coating unit BARC and resist film coating unit RESIST, but allows the atmosphere to be shared between these coating units. Instead, the atmospheres of the two units may be blocked off as appropriate. (12) In the foregoing embodiment, one first blowout unit 61 and one exhaust unit 62 are constructed to block off the atmosphere of each of the transporting spaces A 1 and A 3 (A 2 and A 4 ). The invention is not limited to this. For example, only one of the first blowout unit 61 and exhaust unit 62 may block off atmosphere. Alternatively, a shielding plate may be provided separately from the first blowout unit 61 and exhaust unit 62 for blocking off the atmosphere of each of the upper and lower transporting spaces A. (13) In the foregoing embodiment, the first blowout unit 61 is disposed over each transporting space A, and the exhaust unit 62 disposed under each transporting space. Instead, the first blowout unit 61 or exhaust unit 62 may be disposed laterally of each transporting space A. The first blowout unit 61 and exhaust unit 62 may be shared by the transporting spaces A 1 and A 2 (A 3 and A 4 ) of the same substrate treatment line Lu (Ld). This invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof and, accordingly, reference should be made to the appended claims, rather than to the foregoing specification, as indicating the scope of the invention.

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Patent Citations (374)

    Publication numberPublication dateAssigneeTitle
    US-2010061718-A1March 11, 2010Tokyo Electron LimitedCoating and developing apparatus, coating and developing method, and storage medium
    US-2009142713-A1June 04, 2009Tokyo Electron LimitedSubstrate processing system and substrate processing method
    US-6264748-B1July 24, 2001Tokyo Electron LimitedSubstrate processing apparatus
    US-6491451-B1December 10, 2002Motorola, Inc.Wafer processing equipment and method for processing wafers
    US-6063439-AMay 16, 2000Tokyo Electron LimitedProcessing apparatus and method using solution
    US-2006028630-A1February 09, 2006Canon Kabushiki KaishaLiquid immersion exposure apparatus, method of controlling the same, and device manufacturing method
    US-7072730-B2July 04, 2006Ebara CorporationSubstrate transfer controlling apparatus and substrate transferring method
    US-8034190-B2October 11, 2011Sokudo Co., Ltd.Substrate processing apparatus and substrate processing method
    US-5844662-ADecember 01, 1998Tokyo Electron LimitedResist processing apparatus and a resist processing method
    US-2008158531-A1July 03, 2008Nikon CorporationExposure apparatus, exposure method, and method for producing device
    US-5842917-ADecember 01, 1998United Microelectronics CorprorationAutomated manufacturing plant for semiconductor devices
    JP-2006216614-AAugust 17, 2006Tokyo Electron Ltd, 東京エレクトロン株式会社Coating and developing apparatus
    US-5788868-AAugust 04, 1998Dainippon Screen Mfg. Co., Ltd.Substrate transfer method and interface apparatus
    US-6235634-B1May 22, 2001Applied Komatsu Technology, Inc.Modular substrate processing system
    US-5937223-AAugust 10, 1999Tokyo Electron LimitedProcessing apparatus
    US-5536128-AJuly 16, 1996Hitachi, Ltd.Method and apparatus for carrying a variety of products
    JP-2005101078-AApril 14, 2005Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社Substrate treatment equipment
    US-6879866-B2April 12, 2005Asml Netherlands B.V.Method, computer program product and apparatus for scheduling maintenance actions in a substrate processing system
    US-2004122545-A1June 24, 2004Dainippon Screen Mfg. Co., Ltd.Substrate processing apparatus, operation method thereof and program
    JP-2001093827-AApril 06, 2001Tokyo Electron Ltd, 東京エレクトロン株式会社処理システム
    JP-2004260129-ASeptember 16, 2004Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社Substrate treatment apparatus, substrate carrying method in apparatus and substrate treatment method
    JP-2006335484-ADecember 14, 2006Daifuku Co Ltd, 株式会社ダイフクConveying device
    US-4985722-AJanuary 15, 1991Tokyo Electron Limited, Tel Kyushu LimitedApparatus for coating a photo-resist film and/or developing it after being exposed
    US-6402401-B1June 11, 2002Tokyo Electron LimitedSubstrate processing apparatus and substrate processing method
    US-5788447-AAugust 04, 1998Kokusai Electric Co., Ltd.Substrate processing apparatus
    US-6287025-B1September 11, 2001Tokyo Electron LimitedSubstrate processing apparatus
    US-5963753-AOctober 05, 1999Dainippon Screen Mfg. Co., Ltd.Substrate processing apparatus
    US-2011043773-A1February 24, 2011Tokyo Electron LimitedCoating/developing apparatus and coating/developing method
    JP-2007150071-AJune 14, 2007Tokyo Electron Ltd, 東京エレクトロン株式会社塗布・現像装置及び塗布・現像方法
    US-2012029687-A1February 02, 2012Par Systems, Inc.Robotic storage and retrieval systems
    US-2005030511-A1February 10, 2005Asml Netherlands B.V.Interface unit, lithographic projection apparatus comprising such an interface unit and a device manufacturing method
    US-2008014333-A1January 17, 2008Tokyo Electron LimitedCoating and developing apparatus, substrate processing method, and storage medium
    US-8113141-B2February 14, 2012Semes Co., LtdApparatus for processing a substrate
    US-5430271-AJuly 04, 1995Dainippon Screen Mfg. Co., Ltd.Method of heat treating a substrate with standby and treatment time periods
    US-6889014-B2May 03, 2005Canon Kabushiki KaishaExposure system, device production method, semiconductor production factory, and exposure apparatus maintenance method
    US-7008124-B2March 07, 2006Tokyo Electron LimitedMethod and device for processing substrate
    US-2011211825-A1September 01, 2011Tokyo Electron LimitedCoating and developing apparatus, substrate processing method, and storage medium
    US-8353986-B2January 15, 2013Tokyo Electron LimitedSubstrate processing apparatus
    US-2006201423-A1September 14, 2006Tokyo Electron LimitedCoating/developing device and method
    US-2004061065-A1April 01, 2004Advantest Corporation, Hitachi, Ltd., Canon Kabushiki KaishaElectron beam exposure apparatus, electron beam exposure apparatus calibration method, and semiconductor element manufacturing method
    US-2006286300-A1December 21, 2006Tetsuya Ishikawa, Roberts Rick J, Armer Helen R, Leon Volfovski, Pinson Jay D, Michael Rice, Quach David H, Salek Mohsen S, Robert Lowrance, Weaver William T, Charles Carlson, Chongyang Wang, Jeffrey Hudgens, Harald Herchen, Brian Lue, Backer John ACluster tool architecture for processing a substrate
    US-7675048-B2March 09, 2010Varian Semiconductor Equipment Associates, Inc.Wafer holding robot end effecter vertical position determination in ion implanter system
    US-7069099-B2June 27, 2006Dainippon Screen Mfg. Co., Ltd.Method of transporting and processing substrates in substrate processing apparatus
    US-5297910-AMarch 29, 1994Tokyo Electron Limited, Tokyo Electron Kyushu LimitedTransportation-transfer device for an object of treatment
    US-5275709-AJanuary 04, 1994Leybold AktiengesellschaftApparatus for coating substrates, preferably flat, more or less plate-like substrates
    US-7934880-B2May 03, 2011Tokyo Electron LimitedCoating and developing apparatus, coating and developing method, and storage medium
    US-2005042555-A1February 24, 2005Tokyo Electron LimitedCoating and developing apparatus and pattern forming method
    US-7652276-B2January 26, 2010Tokyo Electron LimitedDefect inspection method, defect inspection apparatus having a mounting table with a substrate thereon and an image pickup device are relatively moved for capturing the image of the substrate, and computer readable storage medium storing a program for performing the method
    JP-2004015021-AJanuary 15, 2004Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社基板処理装置
    US-6558053-B2May 06, 2003Dainippon Screen Mfg. Co., Ltd.Substrate processing apparatus
    US-2006098978-A1May 11, 2006Schuichi Yasuda, Masashi Kanaoka, Koji Kaneyama, Tadashi Miyagi, Kazuhito Shigemori, Toru Asano, Akihiro Hisai, Hiroshi Kobayashi, Tsuyoshi OkumuraSubstrate processing apparatus and substrate processing method
    US-6982102-B2January 03, 2006Tokyo Electron LimitedCoating unit and coating method
    US-7905668-B2March 15, 2011Tokyo Electron LimitedCoating/developing apparatus and method
    US-6758647-B2July 06, 2004Hitachi High-Technologies CorporationSystem for producing wafers
    US-7641406-B2January 05, 2010Sokudo Co., Ltd.Bevel inspection apparatus for substrate processing
    US-6377329-B1April 23, 2002Tokyo Electron LimitedSubstrate processing apparatus
    US-5826129-AOctober 20, 1998Tokyo Electron Limited, Tokyo Electron Kyushu LimitedSubstrate processing system
    US-7017658-B2March 28, 2006Dainippon Screen Mfg. Co., Ltd.Heat processing device
    US-2012015307-A1January 19, 2012Tokyo Electron LimitedCoating and developing apparatus and method, and storage medium
    US-5664254-ASeptember 02, 1997Tokyo Electron LimitedSubstrate processing apparatus and substrate processing method
    JP-2001176792-AJune 29, 2001Dns Korea Co Ltd, ディ エヌ エス コリア カンパニー リミティッド半導体製造のためのフォトリソグラフィ装置
    US-7841072-B2November 30, 2010Tokyo Electron LimitedApparatus and method of application and development
    US-5972110-AOctober 26, 1999Tokyo Electron LimitedResist processing system
    US-2006090849-A1May 04, 2006Kazuyuki Toyoda, Atsuhiko Suda, Issei Makiguchi, Tsutomu Tanaka, Sadayuki Suzuki, Shinichi Nomura, Mitsunori TakeshitaSubstrate processing apparatus
    US-2001013515-A1August 16, 2001Koji Harada, Issei UedaHeat and cooling treatment apparatus and substrate processing system
    US-2011078898-A1April 07, 2011Tokyo Electron LimitedSubstrate processing apparatus
    US-6382895-B1May 07, 2002Anelva CorporationSubstrate processing apparatus
    US-6919001-B2July 19, 2005Intevac, Inc.Disk coating system
    US-7925377-B2April 12, 2011Applied Materials, Inc.Cluster tool architecture for processing a substrate
    US-8708587-B2April 29, 2014Sokudo Co., Ltd.Substrate treating apparatus with inter-unit buffers
    JP-2007227984-ASeptember 06, 2007Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社Substrate processing apparatus
    US-2007172234-A1July 26, 2007Kazuhito Shigemori, Koji Kaneyama, Masashi Kanaoka, Tadashi Miyagi, Shuichi YasudaApparatus for and method of processing substrate
    US-6270306-B1August 07, 2001Applied Materials, Inc.Wafer aligner in center of front end frame of vacuum system
    US-2007274711-A1November 29, 2007Koji Kaneyama, Kazuhito Shigemori, Masashi Kanaoka, Tadashi Miyagi, Shuichi YasudaSubstrate processing apparatus and substrate processing method
    US-7522823-B2April 21, 2009Sokudo Co., Ltd.Thermal processing apparatus, thermal processing method, and substrate processing apparatus
    US-6426303-B1July 30, 2002Tokyo Electron LimitedProcessing system
    US-7001674-B2February 21, 2006Nikon CorporationExposure method, exposure apparatus, and method of production of device
    US-6464789-B1October 15, 2002Tokyo Electron LimitedSubstrate processing apparatus
    US-8731701-B2May 20, 2014Tokyo Electron LimitedSubstrate treatment method and substrate treatment system
    US-5571325-ANovember 05, 1996Dainippon Screen Mfg. Co., Ltd.Subtrate processing apparatus and device for and method of exchanging substrate in substrate processing apparatus
    US-6099643-AAugust 08, 2000Dainippon Screen Mfg. Co., Ltd.Apparatus for processing a substrate providing an efficient arrangement and atmospheric isolation of chemical treatment section
    JP-H0689934-B2November 14, 1994ウルリヒ・グリガ−トマルチバレント放熱器
    US-5858863-AJanuary 12, 1999Hitachi, Ltd.Fabrication system and method having inter-apparatus transporter
    US-6432842-B2August 13, 2002Tokyo Electron LimitedCoating method and coating apparatus
    JP-2004031921-AJanuary 29, 2004Nikon Corp, 株式会社ニコン露光方法、露光装置及びデバイス製造方法
    US-2012084059-A1April 05, 2012Tokyo Electron LimitedData acquisition method of substrate treatment apparatus and sensor substrate
    US-6537835-B2March 25, 2003Sony CorporationMethod of manufacturing semiconductor device and apparatus of automatically adjusting semiconductor pattern
    US-6432842-B1December 31, 1969
    US-6151981-ANovember 28, 2000Costa; Larry J.Two-axis cartesian robot
    US-2006137726-A1June 29, 2006Dainippon Screen Mfg. Co., Ltd.Substrate treating apparatus
    US-5876280-AMarch 02, 1999Tokyo Electron LimitedSubstrate treating system and substrate treating method
    US-2011063588-A1March 17, 2011Kashiyama Masahito, Yukihiko Inagaki, Kazuya Akiyama, Noriaki Yokono, Isao TaniguchiSubstrate processing apparatus, substrate processing system and inspection/periphery exposure apparatus
    US-2011082579-A1April 07, 2011Tokyo Electron LimitedSubstrate processing apparatus, substrate processing method, and storage medium
    US-2008224817-A1September 18, 2008Sokudo Co., Ltd.Interlaced rtd sensor for zone/average temperature sensing
    US-2009070946-A1March 19, 2009Sokudo Co., Ltd.Apparatus for and method of processing substrate
    US-5668733-ASeptember 16, 1997Dainippon Screen Mfg. Co., Ltd.Substrate processing apparatus and method
    US-8220354-B2July 17, 2012Genmark Automation, Inc.Belt-driven robot having extended Z-axis motion
    US-8419341-B2April 16, 2013Brooks Automation, Inc.Linear vacuum robot with Z motion and articulated arm
    US-8612807-B2December 17, 2013Ncr CorporationEntertainment kiosk error handling and troubleshooting method
    JP-2004087675-AMarch 18, 2004Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社Substrate treating device
    US-2006162858-A1July 27, 2006Tokyo Electron LimitedCoating and developing system and coating and developing method
    US-2014152966-A1June 05, 2014Semes Co., Ltd.Facility and method for treating substrate
    US-2008129968-A1June 05, 2008Tokyo Electron LimitedCoating and developing system, coating and developing method and storage medium
    US-2011297085-A1December 08, 2011Tokyo Electron LimitedSubstrate processing apparatus, substrate processing method, and storage medium
    US-6454472-B1September 24, 2002Dns Korea Co., Ltd.Semiconductor manufacturing apparatus for photolithographic process
    US-2005266323-A1December 01, 2005Asml Netherlands B.V.Lithographic apparatus and device manufacturing method
    US-2004050321-A1March 18, 2004Tokyo Electron LimitedSubstrate processing apparatus and substrate processing method
    US-7563042-B2July 21, 2009Tokyo Electron LimitedSubstrate carrying apparatus, substrate carrying method, and coating and developing apparatus
    US-2010126527-A1May 27, 2010Sokudo Co., Ltd.Apparatus for and method of processing substrate subjected to exposure process
    US-2012145073-A1June 14, 2012Sokudo Co., Ltd.Substrate treating apparatus
    US-2010183807-A1July 22, 2010Kim Dong-HunSubstrate processing apparatus and substrate processing method
    US-7801633-B2September 21, 2010Dainippon Screen Mfg. Co., Ltd.Scheduling method and program for a substrate treating apparatus
    US-7497633-B2March 03, 2009Sokudo Co., Ltd.Substrate processing apparatus and substrate processing method
    US-2005061441-A1March 24, 2005Dainippon Screen Mfg. Co., Ltd.Substrate treating apparatus
    US-7323060-B2January 29, 2008Dainippon Screen Mfg. Co., Ltd.Substrate treating apparatus
    US-7661894-B2February 16, 2010Tokyo Electron LimitedCoating and developing apparatus, and coating and developing method
    US-5102283-AApril 07, 1992Martin Balzola ElorzaAutomatic positioner for stores
    US-6287023-B1September 11, 2001Tokyo Electron LimitedProcessing apparatus and method
    US-6590634-B1July 08, 2003Nikon CorporationExposure apparatus and method
    US-5651823-AJuly 29, 1997Semiconductor Systems, Inc.Clustered photolithography system
    US-2008212049-A1September 04, 2008Sokudo Co., Ltd.Substrate processing apparatus with high throughput development units
    US-2004007176-A1January 15, 2004Applied Materials, Inc.Gas flow control in a wafer processing system having multiple chambers for performing same process
    US-2009001071-A1January 01, 2009Sokudo Co., LtdMethod and System for Cooling a Bake Plate in a Track Lithography Tool
    US-7836845-B2November 23, 2010Tokyo Electron LimitedSubstrate carrying and processing apparatus
    US-6752872-B2June 22, 2004Tokyo, Electron LimitedCoating unit and coating method
    US-6511315-B2January 28, 2003Dainippon Screen Mfg. Co., Ltd.Substrate processing apparatus
    US-2006194445-A1August 31, 2006Tokyo Electron LimitedSemiconductor manufacturing apparatus and method
    US-2008304940-A1December 11, 2008Auer-Jongepier Suzan L, Johannes Onvlee, Bartray Petrus R, Luttikhuis Bernardus A J, Plug Reinder T, Segers Hubert MIntegrated post-exposure bake track
    JP-H10144673-AMay 29, 1998Yamaha Corp, ヤマハ株式会社配線形成法
    US-2012145074-A1June 14, 2012Sokudo Co., Ltd.Substrate treating apparatus
    US-5803932-ASeptember 08, 1998Tokyo Electron Limited, Tokyo Electron Kyushu LimitedResist processing apparatus having an interface section including two stacked substrate waiting tables
    US-2002048509-A1April 25, 2002Kazunari Sakata, Yasushi TakeuchiProcessing system for object to be processed
    KR-20070003328-AJanuary 05, 2007세메스 주식회사복층 구조의 반도체 제조 설비 및 그의 처리 방법
    US-8113142-B2February 14, 2012Semes Co., Ltd.Apparatus for processing a substrate
    US-7641405-B2January 05, 2010Sokudo Co., Ltd.Substrate processing apparatus with integrated top and edge cleaning unit
    US-2009165711-A1July 02, 2009Sokudo Co., Ltd.Substrate treating apparatus with substrate reordering
    US-6227786-B1May 08, 2001Tokyo Electron LimitedSubstrate treating apparatus
    US-4409889-AOctober 18, 1983Burleson Maurice LModular clean room
    JP-H10189420-AJuly 21, 1998Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社基板処理装置
    US-6290405-B1September 18, 2001Tokyo Electron LimitedSubstrate processing apparatus
    US-6146083-ANovember 14, 2000Tokyo Electron LimitedSubstrate transferring apparatus and substrate processing apparatus using the same
    US-2010195066-A1August 05, 2010Semes Co., Ltd.System and method for treating substrate
    JP-2007005659-AJanuary 11, 2007Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社Substrate processor
    US-6099598-AAugust 08, 2000Hitachi, Ltd.Fabrication system and fabrication method
    US-2007190437-A1August 16, 2007Koji Kaneyama, Masashi Kanaoka, Tadashi Miyagi, Kazuhito Shigemori, Shuichi Yasuda, Tetsuya HamadaSubstrate processing apparatus
    JP-2000200822-AJuly 18, 2000Tokyo Electron Ltd, 東京エレクトロン株式会社処理システム
    US-5028195-AJuly 02, 1991Tel Sagami LimitedHorizontal/vertical conversion transporting apparatus
    US-6444029-B1September 03, 2002Tokyo Electron LimitedMultistage spin type substrate processing system
    US-2007179658-A1August 02, 2007Tetsuya HamadaSubstrate processing system capable of monitoring operation of substrate processing apparatus
    US-6010570-AJanuary 04, 2000Tokyo Electron LimitedApparatus for forming coating film for semiconductor processing
    US-2007297794-A1December 27, 2007Samsung Electronics Co., Ltd.Photolithography system and method
    US-6116841-ASeptember 12, 2000Tokyo Electron LimitedSubstrate transferring apparatus and substrate processing apparatus using the same
    JP-2000124129-AApril 28, 2000Tokyo Electron Ltd, 東京エレクトロン株式会社処理装置
    JP-H1050794-AFebruary 20, 1998Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社基板処理装置および方法
    US-2003147643-A1August 07, 2003Tokyo Electron LimitedSubstrate processing apparatus and substrate transferring method
    US-2003213431-A1November 20, 2003Dainippon Screen Mfg. Co., Ltd.Substrate treating apparatus
    US-6937917-B2August 30, 2005Dainippon Screen Mfg. Co., Ltd.Substrate processing apparatus, operation method thereof and program
    US-6910497-B2June 28, 2005AlcatelSemiconductor component manufacturing plant with ventilated false floor
    US-6680775-B1January 20, 2004Nikon CorporationSubstrate treating device and method, and exposure device and method
    JP-2004015023-AJanuary 15, 2004Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社基板処理装置およびその方法
    US-2010050940-A1March 04, 2010Tokyo Ohka Kogyo Co., Ltd.Substrate processing system, carrying device and coating device
    US-7317961-B2January 08, 2008Dainippon Screen Mfg. Co., Ltd.Substrate processing apparatus and method of transporting substrates and method of processing substrates in substrate processing apparatus
    US-6466300-B1October 15, 2002Tokyo Electron LimitedSubstrate processing apparatus
    JP-2003224175-AAugust 08, 2003Tokyo Electron Ltd, 東京エレクトロン株式会社Apparatus and method for handling semiconductor
    US-2009044747-A1February 19, 2009Joichi NishimuraSubstrate treating system
    JP-H11340301-ADecember 10, 1999Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社基板処理装置および基板処理方法
    US-6062798-AMay 16, 2000Brooks Automation, Inc.Multi-level substrate processing apparatus
    US-6266125-B1July 24, 2001Tokyo Electron LimitedResist processing method and apparatus
    KR-100698352-B1March 23, 2007동경 엘렉트론 주식회사기판처리장치 및 기판처리방법
    JP-2006245312-ASeptember 14, 2006Hitachi Kokusai Electric Inc, 株式会社日立国際電気Manufacturing method of semiconductor device
    US-7729798-B2June 01, 2010Tokyo Electron LimitedSubstrate processing system, and method of control therefor, control program, and storage medium
    JP-2004200485-AJuly 15, 2004Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社基板処理装置とその動作方法、およびプログラム
    US-2011276166-A1November 10, 2011George AtanasoffMethods and systems for control of a surface modification process
    JP-H09251953-ASeptember 22, 1997Sony Corp, ソニー株式会社Resist development
    US-2006147202-A1July 06, 2006Dainippon Screen Mfg. Co., Ltd.Substrate processing apparatus and substrate processing method
    JP-2004193597-AJuly 08, 2004Tokyo Electron Ltd, 東京エレクトロン株式会社Substrate treatment system, and coating and developing apparatus
    US-6832863-B2December 21, 2004Dainippon Screen Mfg. Co., Ltd.Substrate treating apparatus and method
    KR-20020035758-AMay 15, 2002히가시 데쓰로, 동경 엘렉트론 주식회사액처리방법 및 액처리장치
    US-5177514-AJanuary 05, 1993Tokyo Electron LimitedApparatus for coating a photo-resist film and/or developing it after being exposed
    KR-20060050112-AMay 19, 2006동경 엘렉트론 주식회사기판 처리 장치 기판 처리 방법 및 컴퓨터프로그램
    US-2009165950-A1July 02, 2009Duk-Sik Kim, Joon-Jae LeeApparatus for treating substrate and method for transferring substrate using the same
    US-8154106-B2April 10, 2012Tokyo Electron LimitedCoating and developing system and coating and developing method
    US-8289496-B2October 16, 2012Semes Co., Ltd.System and method for treating substrate
    US-6893171-B2May 17, 2005Dainippon Screen Mfg. Co., Ltd.Substrate treating apparatus
    JP-2002510141-AApril 02, 2002アプライド マテリアルズ インコーポレイテッド真空システムの前端フレームの中心に配したウエハアライナ
    JP-H07283094-AOctober 27, 1995Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社Substrate processing system
    US-2014000514-A1January 02, 2014Sokudo Co., Ltd.Substrate treating apparatus with inter-unit buffers
    US-6485203-B2November 26, 2002Tokyo Electron LimitedSubstrate processing method and substrate processing apparatus
    KR-20040054517-AJune 25, 2004다이닛뽕스크린 세이조오 가부시키가이샤기판 처리 장치, 작동 방법 및 그에 대한 프로그램
    KR-20060092061-AAugust 22, 2006동경 엘렉트론 주식회사Semiconductor manufacturing apparatus and method
    US-5100516-AMarch 31, 1992Yamaha Hatsudoki Kabushiki KaishaHigh volume workpiece handling and chemical treating system
    US-2008037013-A1February 14, 2008Tokyo Electron LimitedMethod and system for determining condition of process performed for coating film before immersion light exposure
    US-2006062282-A1March 23, 2006David WrightMethod for providing packet framing in a DSSS radio system
    US-2010192844-A1August 05, 2010Semes Co., Ltd.Apparatus and method for treating substrate
    US-2002053319-A1May 09, 2002Shuichi NagamineSolution treatment method and solution treatment unit
    US-6807455-B2October 19, 2004Dainippon Screen Mfg. Co. Ltd.System for and method of processing substrate
    US-7335090-B2February 26, 2008Dainippon Screen Mfg. Co., Ltd.Substrate processing apparatus and substrate handling method
    US-6750155-B2June 15, 2004Lam Research CorporationMethods to minimize moisture condensation over a substrate in a rapid cycle chamber
    US-5668056-ASeptember 16, 1997United Microelectronics CorporationSingle semiconductor wafer transfer method and manufacturing system
    JP-2004319767-ANovember 11, 2004Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社基板処理装置
    JP-2003324059-ANovember 14, 2003Tokyo Electron Ltd, 東京エレクトロン株式会社Substrate processing method
    US-5202716-AApril 13, 1993Tokyo Electron Limited, Tokyo Electron Kyushu LimitedResist process system
    US-6461438-B1October 08, 2002Tokyo Electron LimitedHeat treatment unit, cooling unit and cooling treatment method
    US-2009142162-A1June 04, 2009Sokudo Co., Ltd.Substrate treating apparatus with inter-unit buffers
    JP-2004241319-AAugust 26, 2004Sony Corp, ソニー株式会社Film forming device
    US-7686559-B2March 30, 2010Daifuku Co., Ltd.Article transport facility and a method of operating the facility
    US-2008269937-A1October 30, 2008Tokyo Electron LimitedSubstrate processing method, substrate processing system, and computer-readable storage medium
    US-2005135905-A1June 23, 2005Daifuku Co., Ltd.Glass substrate transporting facility
    KR-100634122-B1October 16, 2006동경 엘렉트론 주식회사Substrate processing apparatus and substrate processing method
    US-7809460-B2October 05, 2010Tokyo Electron LimitedCoating and developing apparatus, coating and developing method and storage medium in which a computer-readable program is stored
    JP-H09312323-ADecember 02, 1997Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社Flow control method and flow controller of substrate processor
    US-2012097336-A1April 26, 2012Tokyo Electron LimitedTemplate treatment apparatus and imprint system
    US-2009014126-A1January 15, 2009Sokudo Co., Ltd.Substrate processing apparatus and substrate processing method
    US-6333003-B1December 25, 2001Tokyo Electron LimitedTreatment apparatus, treatment method, and impurity removing apparatus
    US-2014003891-A1January 02, 2014Tokyo Electron LimitedSubstrate processing apparatus
    US-7262829-B2August 28, 2007Tokyo Electron LimitedCoating and developing apparatus and coating and developing method
    US-5976199-ANovember 02, 1999United Microelectronics Corp.Single semiconductor wafer transfer method and manufacturing system
    US-8443513-B2May 21, 2013Tokyo Electron LimitedSubstrate processing apparatus
    US-2012013859-A1January 19, 2012Tokyo Electron LimitedCoating and developing apparatus and method
    US-2012135148-A1May 31, 2012Tokyo Electron LimitedSubstrate treatment system, substrate treatment method, and non-transitory computer storage medium
    US-6161969-ADecember 19, 2000Tokyo Electron LimitedApparatus for processing a substrate
    JP-2007208064-AAugust 16, 2007Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社Substrate-treating device and substrate treatment method
    US-2009000543-A1January 01, 2009Sokudo Co., Ltd.Substrate treating apparatus
    JP-2003338496-ANovember 28, 2003Tokyo Electron Ltd, 東京エレクトロン株式会社基板処理装置
    US-5928390-AJuly 27, 1999Tokyo Electron LimitedVertical processing apparatus
    JP-2004207279-AJuly 22, 2004Rorze Corp, ローツェ株式会社薄板状物製造設備
    US-2007058147-A1March 15, 2007Tetsuya HamadaApparatus for and method of processing substrate subjected to exposure process
    JP-2006269672-AOctober 05, 2006Tokyo Electron Ltd, 東京エレクトロン株式会社Apparatus and method for coating/developing
    US-2009291558-A1November 26, 2009Samsung Electronics Co., Ltd.Multi-chamber system having compact installation set-up for an etching facility for semiconductor device manufacturing
    US-8588950-B2November 19, 2013Hitachi Kokusai Electric Inc.Substrate processing apparatus
    KR-20060097613-ASeptember 14, 2006동경 엘렉트론 주식회사Coating/developing device and method
    US-2009018686-A1January 15, 2009Masahiro Yamamoto, Daigo YamadaScheduling method and program for a substrate treating apparatus
    US-6027262-AFebruary 22, 2000Tokyo Electron LimitedResist process method and system
    CN-1773672-AMay 17, 2006大日本网目版制造株式会社Substrate processing apparatus and substrate processing method
    US-8560108-B2October 15, 2013Tokyo Electron LimitedSubstrate processing apparatus and substrate processing method
    JP-H10335415-ADecember 18, 1998Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社処理時間の設定方法
    US-7549811-B2June 23, 2009Dainippon Screen Mfg. Co., Ltd.Substrate treating apparatus
    US-2009143903-A1June 04, 2009Donald Blust, Thomas DriscollAutomated business system and method of vending and returning a consumer product
    JP-2009076893-AApril 09, 2009Tokyo Electron Ltd, 東京エレクトロン株式会社Coating and developing apparatus, coating and developing method, and storage medium
    US-2012073461-A1March 29, 2012Shoichi Terada, Yoshio Kimura, Takahiro KitanoImprint system, imprint method, and non-transitory computer storage medium
    JP-2000124124-AApril 28, 2000Tokyo Electron Ltd, 東京エレクトロン株式会社基板処理装置
    US-2009139833-A1June 04, 2009Sokudo Co., Ltd.Multi-line substrate treating apparatus
    US-5565034-AOctober 15, 1996Tokyo Electron Limited, Tokyo Electron Kyushu LimitedApparatus for processing substrates having a film formed on a surface of the substrate
    US-6176667-B1January 23, 2001Applied Materials, Inc.Multideck wafer processing system
    US-2004229441-A1November 18, 2004Dainippon Screen Mfg. Co., LtdSubstrate processing apparatus
    US-2010136257-A1June 03, 2010Sokudo Co., Ltd.Substrate processing apparatus
    US-6955595-B2October 18, 2005Lg.Philips Lcd Co., Ltd.Clean room system
    US-7322756-B2January 29, 2008Tokyo Electron LimitedCoating and developing apparatus and coating and developing method
    US-2011208344-A1August 25, 2011Tokyo Electron LimitedSubstrate processing system, substrate processing method and storage medium
    US-8025023-B2September 27, 2011Tokyo Electron LimitedCoating and developing system, coating and developing method and storage medium
    US-5518542-AMay 21, 1996Tokyo Electron Limited, Tokyo Electron Kyushu LimitedDouble-sided substrate cleaning apparatus
    JP-3600711-B2December 15, 2004大日本スクリーン製造株式会社基板処理装置
    US-2009247053-A1October 01, 2009Lg. Phillips Lcd Co., Ltd.Substrate production apparatus for producing a substrate for a display device
    US-2012271444-A1October 25, 2012Tokyo Electron LimitedSubstrate processing apparatus, substrate processing method and storage medium
    JP-2003324139-ANovember 14, 2003Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社Substrate treatment apparatus
    US-2004005149-A1January 08, 2004Dainippon Screen Mfg. Co.,Ltd.Substrate treating apparatus and method
    KR-20050051280-AJune 01, 2005다이닛뽕스크린 세이조오 가부시키가이샤Substrate treating apparatus and method
    US-2009098298-A1April 16, 2009Tokyo Electron LimitedCoater/developer, method of coating and developing resist film, and computer readable storing medium
    US-2008026153-A1January 31, 2008Tokyo Electron LimitedCoating and developing system, coating and developing method and storage medium
    JP-2006228974-AAugust 31, 2006Tokyo Electron Ltd, 東京エレクトロン株式会社半導体製造装置及び半導体製造方法
    US-6698944-B2March 02, 2004Nikon CorporationExposure apparatus, substrate processing unit and lithographic system, and device manufacturing method
    KR-20060033423-AApril 19, 2006세메스 주식회사Photolithography apparatus used in manufacturing semiconductor substrates
    US-2007056514-A1March 15, 2007Tokyo Electron LimitedCoating and developing apparatus
    US-7758341-B2July 20, 2010Snf Solutions, Co., Ltd.Utility apparatus and utility method of substrate processing apparatus
    US-7699021-B2April 20, 2010Sokudo Co., Ltd.Cluster tool substrate throughput optimization
    US-5820679-AOctober 13, 1998Hitachi, Ltd.Fabrication system and method having inter-apparatus transporter
    KR-20060088495-AAugust 04, 2006동경 엘렉트론 주식회사도포·현상 장치
    US-2003131458-A1July 17, 2003Applied Materials, Inc.Apparatus and method for improving throughput in a cluster tool for semiconductor wafer processing
    JP-2006253501-ASeptember 21, 2006Tokyo Electron Ltd, 東京エレクトロン株式会社Coating and developping device, and its manufacturing method
    US-2006011296-A1January 19, 2006Tokyo Electron LimitedSubstrate processing apparatus, substrate processing method, and computer program
    US-2012307217-A1December 06, 2012Dong Ho Kim, Jinyoung Choi, Jaeseung Go, Soomin HwangSystem and method for treating substrate
    KR-20030086900-ANovember 12, 2003다이닛뽕스크린 세이조오 가부시키가이샤Substrate treating apparatus
    JP-H09199568-AJuly 31, 1997Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社Substrate processing equipment
    JP-H10261689-ASeptember 29, 1998Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社Substrate treating apparatus
    JP-2006229183-AAugust 31, 2006Tokyo Electron Ltd, 東京エレクトロン株式会社Coating, developing device and method
    KR-20010029862-AApril 16, 2001히가시 데쓰로, 동경 엘렉트론 주식회사Substrate delivery apparatus and coating and developing processing system
    JP-2004152801-AMay 27, 2004Tokyo Electron Ltd, 東京エレクトロン株式会社基板処理装置
    US-2012013730-A1January 19, 2012Tokyo Electron LimitedSubstrate processing apparatus, substrate processing method and non-transitory computer storage medium
    JP-2005123249-AMay 12, 2005Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社Substrate processing apparatus and its method
    US-2007219660-A1September 20, 2007Tomohiro Kaneko, Akira MiyataSubstrate transporting and processing apparatus, fault management method for substrate transport and processing apparatus, and storage medium storing fault management program
    US-2003079957-A1May 01, 2003Tetsunori Otaguro, Kazuyuki Matsumura, Takafumi IseriWork conveying system
    JP-2003059810-AFebruary 28, 2003Nec Kansai Ltd, 関西日本電気株式会社薬液処理装置
    US-2010191362-A1July 29, 2010Tokyo Electron LimitedCoating and developing apparatus
    US-2012086142-A1April 12, 2012Tokyo Electron LimitedImprint system, imprint method, and non-transitory computer storage medium
    US-7279067-B2October 09, 2007Tokyo Electron LimitedPort structure in semiconductor processing system
    US-6338582-B1January 15, 2002Tokyo Electron LimitedSubstrate delivery apparatus and coating and developing processing system
    US-2006201615-A1September 14, 2006Tokyo Electron LimitedCoating and developing system
    JP-2003309160-AOctober 31, 2003Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社基板処理装置用ユニットおよび基板処理装置並びにその装置の組立方法
    US-5672205-ASeptember 30, 1997Tokyo Electron Limited, Tokyo Electron Kyushu LimitedCoating apparatus
    US-7525650-B2April 28, 2009Dainippon Screen Mfg., Co., Ltd.Substrate processing apparatus for performing photolithography
    JP-H0485812-AMarch 18, 1992Tokyo Electron Kyushu Kk, Tokyo Electron LtdManufacturing device for semiconductor
    US-5725664-AMarch 10, 1998Tokyo Electron Limited, Tokyo Electron Kyushu LimitedSemiconductor wafer processing apparatus including localized humidification between coating and heat treatment sections
    JP-H0945613-AFebruary 14, 1997Tokyo Electron Kyushu Kk, Tokyo Electron Ltd, 東京エレクトロン九州株式会社, 東京エレクトロン株式会社Treatment system
    US-2005069400-A1March 31, 2005Peter Dickey, Raoul Standt, Maroney John EdwardCartridge transport assembly
    US-6210481-B1April 03, 2001Tokyo Electron LimitedApparatus and method of cleaning nozzle and apparatus of processing substrate
    JP-2004046450-AFebruary 12, 2004Fujitsu Ten Ltd, 富士通テン株式会社救急搬送システム
    JP-H09148240-AJune 06, 1997Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社基板処理装置
    JP-2005243690-ASeptember 08, 2005Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社Substrate processing apparatus
    JP-H10294351-ANovember 04, 1998Sharp Corp, シャープ株式会社Clean box used for manufacturing semiconductor device, system for manufacturing semiconductor device, and manufacture of the same
    US-7241061-B2July 10, 2007Tokyo Electron LimitedCoating and developing system and coating and developing method
    US-2011242508-A1October 06, 2011Tokyo Electron, LimitedInterface system
    US-2009060480-A1March 05, 2009Sokudo Co., Ltd.Method and system for controlling bake plate temperature in a semiconductor processing chamber
    US-2006104635-A1May 18, 2006Dainippon Screen Mfg. Co., Ltd.Substrate processing apparatus and substrate processing method
    US-6007629-ADecember 28, 1999Dainippon Screen Mfg. Co., Ltd.Substrate processing apparatus
    US-2006134330-A1June 22, 2006Applied Materials, Inc.Cluster tool architecture for processing a substrate
    US-2009165712-A1July 02, 2009Sokudo Co., Ltd.substrate treating apparatus with parallel substrate treatment lines
    JP-H10146744-AJune 02, 1998Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社基板処理装置及び方法
    US-2008070164-A1March 20, 2008Tokyo Electron LimitedWet-processing apparatus, wet-processing method and storage medium
    JP-2009099577-AMay 07, 2009Tokyo Electron Ltd, 東京エレクトロン株式会社Coater/developer, method of coating and developing, and storing medium
    US-2002011207-A1January 31, 2002Shigeyuki Uzawa, Izumi TsukamotoExposure apparatus, coating/developing system, device manufacturing system, device manufacturing method, semiconductor manufacturing factory, and exposure apparatus maintenance method
    JP-2006203075-AAugust 03, 2006Tokyo Electron Ltd, 東京エレクトロン株式会社Coating and developing apparatus and its method
    JP-H11251405-ASeptember 17, 1999Tokyo Electron Ltd, 東京エレクトロン株式会社Substrate treating equipment
    US-2007048979-A1March 01, 2007Tokyo Electron LimitedHeating apparatus, and coating and developing apparatus
    US-7281869-B2October 16, 2007Tokyo Electron LimitedCoating and developing system and coating and developing method
    US-5677758-AOctober 14, 1997Mrs Technology, Inc.Lithography System using dual substrate stages
    JP-H085812-B2January 24, 1996三新化学工業株式会社酸アミド化合物の製造方法
    JP-H065689-B2January 19, 1994富士電機株式会社超音波ボンデングツール
    JP-2006287178-AOctober 19, 2006Tokyo Electron Ltd, 東京エレクトロン株式会社Application/development device
    US-2003216053-A1November 20, 2003Akira MiyataMethod and device for processing substrate
    JP-H10209241-AAugust 07, 1998Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社基板搬送装置およびそれを備えた基板処理装置
    JP-2005093920-AApril 07, 2005Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社基板処理装置
    KR-20060085188-AJuly 26, 2006동경 엘렉트론 주식회사도포 현상 장치 및 그 방법
    KR-20050049935-AMay 27, 2005세메스 주식회사기판세정시스템
    US-2009149982-A1June 11, 2009Makio Higashi, Akira Miyata, Shinichi SekiSubstrate processing apparatus, substrate processing method, and computer program
    JP-H113581-AJanuary 06, 1999Sony Corp, ソニー株式会社Cap opening and closing device and method
    US-7537401-B2May 26, 2009Lg Display Co., Ltd.Photo apparatus and method
    US-7645081-B2January 12, 2010Tokyo Electron LimitedCoating and developing apparatus, coating and developing method, and storage medium
    US-2001013161-A1August 16, 2001Tokyo Electron LimitedSubstrate processing apparatus and substrate processing method
    US-6752543-B2June 22, 2004Dainippon Screen Mfg. Co. Ltd.Substrate processing apparatus
    US-2004182318-A1September 23, 2004Dainippon Screen Mfg. Co., Ltd.Substrate processing apparatus and method of transporting substrates and method of processing substrates in substrate processing apparatus
    JP-2000012443-AJanuary 14, 2000Tokyo Electron Ltd, 東京エレクトロン株式会社多段スピン型基板処理システム
    KR-20070007262-AJanuary 15, 2007동경 엘렉트론 주식회사현상 장치 및 현상 방법
    JP-H08162514-AJune 21, 1996Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社基板処理装置および基板処理方法
    US-7651306-B2January 26, 2010Applied Materials, Inc.Cartesian robot cluster tool architecture
    US-8342761-B2January 01, 2013Tokyo Electron LimitedCoating/developing apparatus and coating/developing method
    KR-100387418-B1June 18, 2003한국디엔에스 주식회사A spinner system in use the process of fabricating semiconductor device
    JP-2007158260-AJune 21, 2007Tokyo Electron Ltd, 東京エレクトロン株式会社Application and development apparatus, application and development method, and computer program
    US-2006219171-A1October 05, 2006Tokyo Electron LimitedSubstrate processing apparatus
    US-2007128529-A1June 07, 2007Tetsuji KazaanaExposure method and apparatus, coating apparatus for applying resist to plural substrates, and device manufacturing method
    JP-2000100886-AApril 07, 2000Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社Wafer treatment device
    JP-2007067178-AMarch 15, 2007Tokyo Electron Ltd, 東京エレクトロン株式会社Heating apparatus, coating apparatus, and developing apparatus
    JP-H03211749-ASeptember 17, 1991Tokyo Electron Ltd, Tokyo Erekutoron Kyushu KkSemiconductor manufacturing device
    US-7819079-B2October 26, 2010Applied Materials, Inc.Cartesian cluster tool configuration for lithography type processes
    JP-2005057294-AMarch 03, 2005Asml Netherlands Bv, エイエスエムエル ネザランドズ ベスローテン フエンノートシャップInterface unit, lithographic projector equipped with interface, and method of manufacturing device
    US-7871211-B2January 18, 2011Tokyo Electron LimitedCoating and developing system, coating and developing method and storage medium
    US-7692764-B2April 06, 2010Nikon CorporationExposure apparatus, operation decision method, substrate processing system, maintenance management method, and device manufacturing method
    JP-2005167083-AJune 23, 2005Daifuku Co Ltd, 株式会社ダイフクConveyance equipment for glass substrate
    JP-H1116978-AJanuary 22, 1999Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社Substrate treatment equipment
    US-8631809-B2January 21, 2014Sokudo Co., Ltd.Substrate processing apparatus
    US-2003098966-A1May 29, 2003Canon Kabushiki KaishaStage system and stage driving method for use in exposure apparatus
    US-2001031147-A1October 18, 2001Hideyuki Takamori, Kiyohisa Tateyama, Kengo Mizosaki, Noriyuki Anai, Mitsuhiro Sakai, Shinobu Tanaka, Yoichi Honda, Yuji ShimomuraSubstrate process method and substrate process apparatus
    US-2009139450-A1June 04, 2009Sokudo Co., Ltd.Multi-story substrate treating apparatus with flexible transport mechanisms
    JP-2007287887-ANovember 01, 2007Tokyo Electron Ltd, 東京エレクトロン株式会社Coating-developing apparatus, coating and developing meth0d, and memory medium
    US-8268384-B2September 18, 2012Tokyo Electron LimitedSubstrate processing apparatus and substrate processing method
    US-7604424-B2October 20, 2009Sokudo Co., Ltd.Substrate processing apparatus
    JP-H01241840-ASeptember 26, 1989Canon Inc, Canon Sales Co IncSubstrate processor
    US-2014342558-A1November 20, 2014Sokudo Co., Ltd.Substrate treating apparatus with substrate reordering
    JP-2000269297-ASeptember 29, 2000Tatsumo Kk, Tokyo Ohka Kogyo Co Ltd, タツモ株式会社, 東京応化工業株式会社処理ユニット構築体
    KR-20030087417-ANovember 14, 2003엘지전자 주식회사Apparatus and method for controlling a power off automatically in Persnal Digital Assitant
    US-8545118-B2October 01, 2013Sokudo Co., Ltd.Substrate treating apparatus with inter-unit buffers
    JP-2009164256-AJuly 23, 2009Sokudo Co Ltd, 株式会社Sokudo基板処理装置
    US-8851008-B2October 07, 2014Sokudo Co., Ltd.Parallel substrate treatment for a plurality of substrate treatment lines
    US-8480319-B2July 09, 2013Tokyo Electron LimitedCoating and developing apparatus, coating and developing method and non-transitory tangible medium
    US-7053990-B2May 30, 2006Asml Holding N.V.System to increase throughput in a dual substrate stage double exposure lithography system
    JP-2000049089-AFebruary 18, 2000Tokyo Electron Ltd, 東京エレクトロン株式会社レジスト処理方法及びレジスト処理装置
    JP-2000331922-ANovember 30, 2000Tokyo Electron Ltd, 東京エレクトロン株式会社基板処理装置
    US-7245348-B2July 17, 2007Tokyo Electron LimitedCoating and developing system and coating and developing method with antireflection film and an auxiliary block for inspection and cleaning
    JP-2004311714-ANovember 04, 2004Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社基板処理装置
    JP-2004304003-AOctober 28, 2004Tokyo Electron Ltd, 東京エレクトロン株式会社処理システム
    US-2007280680-A1December 06, 2007Yong Hun Kim, Jin Woo SeoPhoto apparatus and method
    US-2006024446-A1February 02, 2006Dainippon Screen Mfg. Co., Ltd.Substrate processing apparatus and substrate processing method
    JP-H1074822-AMarch 17, 1998Dainippon Screen Mfg Co Ltd, 大日本スクリーン製造株式会社基板処理装置

NO-Patent Citations (88)

    Title
    Advisory Action for U.S. Appl. No. 12/343,292 mailed Oct. 12, 2012, 3 pages.
    Argument in the Trial for Patent Invalidation for corresponding Korean Patent No. 10-1170211 dated Feb. 27, 2014, 21 pages.
    Argument in the Trial for Patent Invalidation for corresponding Korean Patent No. 10-1213284, dated Dec. 20, 2013, 19 pages.
    Argument in the Trial for Patent Invalidation for corresponding Korean Patent No. 10-1276946 dated May 28, 2014, 45 pages.
    Decision of Patent for corresponding Japanese Application No. 2007-310677 dated Oct. 16, 2012, 3 pages.
    English translation of JP 10-2006-0033423, published Apr. 2006.
    Final Office Action for U.S. Appl. No. 12/163,951 mailed Jan. 19, 2012, 22 pages.
    Final Office Action for U.S. Appl. No. 12/324,788 mailed Dec. 7, 2011, 26 pages.
    Final Office Action for U.S. Appl. No. 12/324,788 mailed on Nov. 6, 2014, 44 pages.
    Final Office Action for U.S. Appl. No. 12/324,802 mailed Apr. 20, 2012, 14 pages.
    Final Office Action for U.S. Appl. No. 12/324,802 mailed on Oct. 22, 2014, 24 pages.
    Final Office Action for U.S. Appl. No. 12/343,292 mailed Jun. 1, 2012, 15 pages.
    Final Office Action for U.S. Appl. No. 12/343,292 mailed on Nov. 5, 2014, 20 pages.
    Final Office Action for U.S. Appl. No. 12/343,302 mailed Apr. 12, 2012, 33 pages.
    Final Office Action for U.S. Appl. No. 13/401,625 mailed Sep. 19, 2013, 11 pages.
    Final Office Action for U.S. Appl. No. 13/401,644 mailed Nov. 22, 2013, 20 pages.
    Final Office Action for U.S. Appl. No. 13/401,644 mailed on Dec. 1, 2014, 20 pages.
    Information Statement for corresponding Japanese Patent Application No. 2007-310676 dated Jan. 15, 2013, 4 pages.
    Information Statement for corresponding Japanese Patent Application No. 2012-118583 dated May 16, 2014, 22 pages.
    Invalidation Trial for corresponding Korean Application No. 10-1010086 dated Apr. 25, 2011, 68 pages.
    Invalidation Trial for corresponding Korean Patent No. 10-1001511 received on Apr. 13, 2011, 53 pages.
    Invalidation Trial for corresponding Korean Patent No. 10-1036420 received on Sep. 27, 2011, 36 pages.
    Invalidation Trial for corresponding Korean Patent No. 10-1047799 (Korean Patent application No. 10-2008-132304) received on Nov. 16, 2011, 69 pages.
    Invalidation Trial for corresponding Korean Patent No. 10-1170211 dated Aug. 7, 2013, 26 pages.
    Invalidation Trial for corresponding Korean Patent No. 10-1213284 dated Jul. 3, 2013, 31 pages.
    Invalidation Trial for corresponding Korean Patent No. 10-1276946, dated Nov. 12, 2013, 52 pages.
    Invalidation trial for corresponding Taiwanese Patent No. 97124376 dated Jul. 30, 2013, 43 pages.
    Machine translation of KR 10-2006-0033423 A, published Apr. 19, 2006.
    Non-Final Office Action for U.S. Appl. No. 12/163,951 mailed Jul. 11, 2011, 18 pages.
    Non-Final Office Action for U.S. Appl. No. 12/324,788 mailed May 27, 2011, 41 pages.
    Non-Final Office Action for U.S. Appl. No. 12/324,788 mailed on Apr. 4, 2014, 30 pages.
    Non-Final Office Action for U.S. Appl. No. 12/324,794 mailed Feb. 3, 2012, 8 pages.
    Non-Final Office Action for U.S. Appl. No. 12/324,802 mailed on Apr. 7, 2014, 17 pages.
    Non-Final Office Action for U.S. Appl. No. 12/324,802 mailed Sep. 14, 2011, 13 pages.
    Non-Final Office Action for U.S. Appl. No. 12/343,292 mailed Oct. 28, 2011, 12 pages.
    Non-Final Office Action for U.S. Appl. No. 12/343,292 mailed on Jun. 3, 2015, 25 pages.
    Non-Final Office Action for U.S. Appl. No. 12/343,302 mailed Aug. 19, 2011, 26 pages.
    Non-Final Office Action for U.S. Appl. No. 12/343,302 mailed on Apr. 10, 2014, 22 pages.
    Non-Final Office Action for U.S. Appl. No. 13/401,625 mailed Mar. 14, 2013, 8 pages.
    Non-Final Office Action for U.S. Appl. No. 13/401,625 mailed on Dec. 9, 2014, 16 pages.
    Non-Final Office Action for U.S. Appl. No. 13/401,625 mailed on Mar. 28, 2014, 11 pages.
    Non-Final Office Action for U.S. Appl. No. 13/401,644 mailed Jun. 21, 2013, 16 pages.
    Non-Final Office Action for U.S. Appl. No. 13/401,644 mailed on Apr. 4, 2014, 10 pages.
    Notice of Allowance for corresponding Korean application No. 10-2010-0105888 dated Apr. 22, 2011, 3 pages.
    Notice of Allowance for corresponding Korean Patent Application No. 10-2008-0132009 dated Jun. 22, 2012, 3 pages.
    Notice of Allowance for corresponding Korean Patent Application No. 10-2012-0005204 dated Jan. 22, 2014, 3 pages.
    Notice of Allowance for U.S. Appl. No. 12/163,951 mailed on Jul. 10, 2014, 9 pages.
    Notice of Allowance for U.S. Appl. No. 12/324,794 mailed May 29, 2013, 7 pages.
    Notice of Allowance for U.S. Appl. No. 12/324,802 mailed on Jun. 26, 2015, 20 pages.
    Notice of Allowance for U.S. Appl. No. 13/401,625 mailed on Jun. 16, 2015, 15 pages.
    Notice of Allowance for U.S. Appl. No. 13/401,644 mailed on Jun. 29, 2015, 15 pages.
    Notice of Allowance for U.S. Appl. No. 14/011,993 mailed Oct. 7, 2013, 11 pages.
    Notice of Allowance of Korean Application No. 10-2008-0118967 dated Oct. 21, 2010, 2 pages total.
    Office Action for corresponding Chinese Application No. 20081010225036.7 dated Sep. 18, 2009, 4 pages.
    Office Action for corresponding Japanese Application No. 2007-172496 dated Sep. 27, 2011, 4 pages.
    Office Action for corresponding Japanese Application No. 2007-310675 dated Jul. 31, 2012, 3 pages.
    Office Action for corresponding Japanese Application No. 2007-310676 dated May 8, 2012, 3 pages.
    Office Action for corresponding Japanese Application No. 2007-310677 dated May 8, 2012, 4 pages.
    Office Action for corresponding Japanese Application No. 2007-340427 dated Oct. 4, 2011, 2 pages.
    Office Action for corresponding Japanese Application No. 2007-340428 dated Apr. 24, 2012, 3 pages.
    Office Action for corresponding Japanese Application No. 2007-340428 dated Oct. 4, 2011, 2 pages.
    Office Action for corresponding Japanese Application No. 2008-076608 dated Jan. 17, 2012, 4 pages.
    Office Action for corresponding Japanese Application No. 2008-076610 dated Jan. 10, 2012, 2 pages.
    Office Action for corresponding Japanese Application No. 2008-076611 dated Jan. 10, 2012.
    Office Action for corresponding Japanese Patent Application No. 2007-340430 dated Dec. 18, 2012, 3 pages.
    Office Action for corresponding Japanese Patent Application No. 2008-327897 dated Nov. 6, 2012, 4 pages.
    Office Action for corresponding Japanese Patent Application No. 2011-257538 dated Jul. 2, 2013, 3 pages.
    Office Action for corresponding Japanese Patent Application No. 2011-257538, dated Dec. 3, 2013, 3 pages.
    Office Action for corresponding Japanese Patent Application No. 2011-265835 dated Apr. 23, 2013, 3 pages.
    Office Action for corresponding Japanese Patent Application No. 2012-118583 dated Jun. 24, 2014, 2 pages.
    Office Action for corresponding Japanese Patent Application No. 2012-118584 dated Oct. 22, 2013, 2 pages.
    Office Action for corresponding Japanese Patent Application No. 2012-118585 dated Jun. 25, 2013, 3 pages.
    Office Action for corresponding Korean Application No. 10-2008-0060084 dated Mar. 9, 2010, 5 pages.
    Office Action for corresponding Korean Application No. 10-2008-0132009 dated Jan. 18, 2011, 5 pages.
    Office Action for corresponding Korean Application No. 10-2008-0132009 dated Jul. 21, 2011, 5 pages.
    Office Action for corresponding Korean Application No. 10-2008-0132304 mailed Oct. 25, 2010, 4 pages.
    Office Action for corresponding Korean Patent Application No. 10-2012-0005204 dated Nov. 1, 2012, 6 pages.
    Office Action for corresponding Taiwanese Application No. 097150911 dated Apr. 10, 2012, 6 pages.
    Office Action for corresponding Taiwanese Application No. 097150912 dated Jun. 1, 2012, 6 pages.
    Office Action for corresponding Taiwanese Patent Application No. 101118484 dated Feb. 26, 2015, 15 pages.
    Restriction Requirement for U.S. Appl. No. 12/163,951 mailed Feb. 3, 2014, 7 pages.
    Restriction Requirement for U.S. Appl. No. 12/343,292 mailed on Apr. 10, 2014, 6 pages.
    Supplemental Notice of Allowance for U.S. Appl. No. 14/011,993 mailed on Apr. 1, 2014, 2 pages.
    Trial Decision for corresponding Korean Patent No. 10-1047799 dated Jun. 25, 2013, 125 pages.
    Trial for Patent Invalidation for corresponding Korean Patent Application No. 10-1432358 dated Nov. 18, 2014, 54 pages.
    Trial for Patent Invalidation for corresponding Korean Patent Application No. 10-1432358, dated May 22, 2015, 60 pages.
    U.S. Appl. No. 14/011,993, filed Aug. 28, 2013 by Ogura et al.
    U.S. Appl. No. 14/447,409, filed Jul. 30, 2014 by Ogura et al.

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